Study of a CMOS-JFET-bipolar radiation hard analog-digital technology suitable for high energy physics electronics

Dentan, M.; Delagnes, É.; Fourches, N.; Rouger, M.; Habrard, M.C.; Blanquart, L.; Delpierre, P.; Potheau, R.; Truche, R.; Blanc, J.P.; Delevoye, E.; Gautier, J.; Pelloie, J.L.; Pontcharra, J. de; Flament, O.; Leray, J.L.; Martin, J.L.; Montaron, J.; Musseau, O.

doi:10.1109/23.273505

Cited by 44 publications

(8 citation statements)

References 3 publications

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“…In the early development of the LHC experiments, several integrated circuit technologies aimed specifically at applications under radiation have been considered [5][6] [7], among which the DMILL technology [8], originally developed at LETI and then transferred to industry. Early on, it offered complementary MOS, JFET and bipolar transistors, later only CMOS and bipolar devices.…”

Section: A Integrated Radiation Fluxmentioning

confidence: 99%

How chips helped discover the Higgs boson at CERN

Snoeys¹

2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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Integrated circuits and devices revolutionized particle physics experiments, and have been a cornerstone in the recent discovery of the Higgs boson by the ATLAS and CMS experiments at the Large Hadron Collider at CERN. Particles are accelerated and brought into collision at specific interaction points. Detectors are giant cameras, about 40 m long by 20 m in diameter, constructed around these interaction points to take pictures of collision products as they fly away from the collision point. They contain millions of channels, often implemented as reverse biased silicon pin diode arrays covering areas of up to 200 m 2 in the center of the experiment, generating a small (~1fC) electric charge upon particle traversals. Integrated circuits provide the readout, and accept collision rates of about 40 MHz with on-line selection of potentially interesting events before data storage. Power consumption directly impacts the measurement quality as it governs the amount of material present in the detector. Radiation tolerance has to exceed space requirements by orders of magnitude. The presence of tens of thousands of chips in a single system requires special attention to uniformity, robustness and redundancy.

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Section: A Integrated Radiation Fluxmentioning

confidence: 99%

How chips helped discover the Higgs boson at CERN

Snoeys¹

2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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“…In Fig. 5, the magnitude of interface-state growth vs. dose is seen to vary widely in the examples given [9,14,19]. While methods of controlling oxide trapped charge are well-known [7] the authors of these papers give no clues as to how interface state growth can be controlled or predicted.…”

Section: Essentials Of Analysismentioning

confidence: 99%

Mapping CMOS radiation tolerance data on a 4-lane chart

Holmes-Siedle

Adams²

1994

IEEE Trans. Nucl. Sci.

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An analysis is made of the growth of threshold voltage as a function of radiation dose in a very wide range of Complementary Metal-Oxide Semiconductor (CMOS) devices, all the way from low (kilorad) to very high (gigarad) doses. It is found that such results can be organized into four LANES OR CORRIDORS on the growth curve diagram. The resulting FOUR-LANE CLASSIFICATION is useful in selecting CMOS technologies and offers a new terminology for describing the radiation tolerance of ICs, namely "Old Soft, New Soft, Tolerant and Very Tolerant". The form of the lanes, though arrived at empirically, is consistent with the current theory of radiation response of MOS structures. The position of a device test result in this framework is a useful indication of the suitability of a device for use in a given radiation environment and could form the basis of a "league table", used to assess the performance of "hardening laboratories" around the world and as a reference source for the properties of thin-film oxide materials.

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“…The ABCD3T chip is produced in the DMILL radiation-hardened BiCMOS [5] process employing npn bipolar transistor in the input stage. Due to the high expected neutron fluence extensive studies of bulk damage effects in readout electronics have been performed.…”

Section: Introductionmentioning

confidence: 99%

Bulk damage in DMILL npn bipolar transistors caused by thermal neutrons versus protons and fast neutrons

Mandić

Cindro

Kramberger

et al. 2004

IEEE Trans. Nucl. Sci.

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DMILL bipolar transistors (npn) were exposed to 24 GeV protons and fast and thermal neutrons to fluences up to 6 10 14 n/cm 2 . Transistor common emitter current gain ( = I collector I base ) was measured after irradiations. It was found that degradation scales as 1(1 ) = k T 8 T where 8 T is the fluence of thermal neutrons and as 1(1 ) = k eq 8 eq , with 8 eq 1-MeV equivalent fluence, if transistors are irradiated with protons or fast neutrons. Large damage factor k T 3 k eq was measured. Thermal neutrons do not have sufficient energy to displace a Si atom. Their damage mechanism is, therefore, identified with 10 B(n ) 7 Li reaction from which energetic and Li particles produce bulk damage in the base of the device. Boron is used as the base dopant in these transistors having also highly doped regions below base contacts. Irradiations with neutrons with energies distributed from thermal to fast show that gain degradation adds up as 1(1 ) = k T 8 T + k eq 8 eq .

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Study of a CMOS-JFET-bipolar radiation hard analog-digital technology suitable for high energy physics electronics

Cited by 44 publications

References 3 publications

How chips helped discover the Higgs boson at CERN

How chips helped discover the Higgs boson at CERN

Mapping CMOS radiation tolerance data on a 4-lane chart

Bulk damage in DMILL npn bipolar transistors caused by thermal neutrons versus protons and fast neutrons

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