Study of Current Density Influence on Bond Wire Degradation Rate in SiC MOSFET Modules

Luo, Haoze; Iannuzzo, Francesco; Baker, Nick; Blaabjerg, Frede; Li, Wuhua; He, Xiangning

doi:10.1109/jestpe.2019.2920715

Cited by 39 publications

(5 citation statements)

References 40 publications

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“…Common package-level failures for devices mainly comprise bond-wire failures and solder fatigue [34], as shown in Figure 2. This type of failure primarily stems from thermo-mechanical stresses [35], relative humidity stresses [36], and high current density stresses [37] during device operation, with thermo-mechanical stresses being dominating. There are two main failure mechanisms of bond wires [40].…”

Section: Main Failure Modes and Characterization Parametersmentioning

confidence: 99%

Failure Characterization of Discrete SiC MOSFETs under Forward Power Cycling Test

Huang,

Singh,

Liu

et al. 2024

Energies

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Silicon carbide (SiC)-based metal–oxide–semiconductor field-effect transistors (MOSFETs) hold promising application prospects in future high-capacity high-power converters due to their excellent electrothermal characteristics. However, as nascent power electronic devices, their long-term operational reliability lacks sufficient field data. The power cycling test is an important experimental method to assess packaging-related reliability. In order to obtain data closest to actual working conditions, forward power cycling is utilized to carry out SiC MOSFET degradation experiments. Due to the wide bandgap characteristics of SiC MOSFETs, the short-term drift of the threshold voltage is much more serious than that of silicon (Si)-based devices. Therefore, an offline threshold voltage measurement circuit is implemented during power cycling tests to minimize errors arising from this short-term drift. Different characterizations are performed based on power cycling tests, focused on measuring the on-state resistance, thermal impedance, and threshold voltage of the devices. The findings reveal that the primary failure mode under forward power cycling tests, with a maximum junction temperature of 130 ∘C, is bond-wire degradation. Conversely, the solder layer and gate oxide exhibit minimal degradation tendencies under these conditions.

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Section: Main Failure Modes and Characterization Parametersmentioning

confidence: 99%

Failure Characterization of Discrete SiC MOSFETs under Forward Power Cycling Test

Huang,

Singh,

Liu

et al. 2024

Energies

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“…The gate oxide layer degradation is the most significant failure for silicon carbide devices. The threshold voltage deviation caused by gate oxide layer degradation in the SiC MOSFET has attracted widespread attention from different scholars [25,26].…”

Section: Chip Failure Mechanismmentioning

confidence: 99%

Research on transformer based online condition monitoring method for IPM

Tang,

Zhao,

Tan

et al. 2024

Meas. Sci. Technol.

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The Intelligent Power Module (IPM) has the integrated packaging, leading to the advantages of convenient use, safety and reliability. However, once it fails, it will cause the whole power supply system to be inoperative, and it is necessary to perform online Condition Monitoring (CM) of the IPM. In this paper, we extract the aging characteristics such as dynamic equivalent resistance, peak-to-peak value, switching frequency, and turn-off time only from the voltage and current of IPM drain-source port, and then propose a non-intrusive online CM method for the IPM based on the Transformer Neural Network (TNN). We analyse the internal aging mechanism of the IPM, the changing law of aging features, and construct multi-dimensional aging fusion features, and then the TNN model is used to monitor early parameters drift of multi-dimensional fusion feature vectors and realize the accurate online prediction of IPM health condition. The experimental analysis results show that the fault prediction accuracy reaches 96%, and can realize the health CM under the condition of noise interference, weak aging features and few external observable points.

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“…CTE mismatch at bond-wire can cause bond-wire lift-off and heel crack, which increases on-resistance [41], [42]. In addition to the thermal cycle, a high drain-current can accelerate bond-wire aging by expanding the internal void in Al bond-wires [43], [44]. CTE mismatch at die attachment solder can increase the junction-to-case thermal resistance and change transient thermal response [45], [46] Surface Reconstruction (After Aging) [19] Stacking Fault (Cross Sectional PL Image) [31] Stacking Fault (Cross Sectional SEM Image) [31] Reconstruction of Metallization (Before Aging) [30] Reconstruction of Metallization (After Aging) [30] SiO2 Crack [32] DBC translates to plastic deformation at high junction temperatures [47], [48].…”

Section: Degradation Mechanisms and Accelerated Lifetime Tests Of Sic...mentioning

confidence: 99%

AC Power Cycling Test Setup and Condition Monitoring Tools for SiC-Based Traction Inverters

Farhadi

Vankayalapati

Sajadi

et al. 2023

IEEE Trans. Veh. Technol.

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AC power cycling tests allow the most realistic reliability assessment by applying close to real stress to the device or module under test to meet functional safety standards, which is highly critical for traction applications. This paper presents a comprehensive guideline and shares critical know-how to develop a 120 KVA AC power cycling test setup for high-power Silicon Carbide (SiC) modules. As of today, traction applications can not generate an early warning signal for drivers to replace critical components on time. For this purpose, the suitable precursors for all dominant failure mechanisms are discussed, and the corresponding condition monitoring tools are proposed to monitor the device aging on power converters. These condition monitoring tools are integrated into the built-in desaturation protection circuit of the electric vehicle (EV) gate driver for low-cost, practical implementation. The on-resistance of all twelve switches is monitored online as a temperature-sensitive electrical parameter (TSEP) to measure the junction temperature of the devices. To avoid heavy processing load in the microcontroller, the out-of-order equivalent time sampling technique is developed for data sampling, which leads to a measurement error of less than 1.5%. In addition, the design considerations regarding common mode noise and aging effect on DESAT protection are investigated, and experimental findings are presented.

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Study of Current Density Influence on Bond Wire Degradation Rate in SiC MOSFET Modules

Cited by 39 publications

References 40 publications

Failure Characterization of Discrete SiC MOSFETs under Forward Power Cycling Test

Failure Characterization of Discrete SiC MOSFETs under Forward Power Cycling Test

Research on transformer based online condition monitoring method for IPM

AC Power Cycling Test Setup and Condition Monitoring Tools for SiC-Based Traction Inverters

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