Study of digital/analog performance parameters of misaligned gate recessed double gate junctionless field-effect-transistor for circuit level application

Abstract

In this work, the effect of gate misalignment towards the source and drain ends for 20 nm recessed double gate junctionless field-effect-transistor (R_DGJLFET) have been studied on various digital and analog performance parameters from device to circuit level while setting the simulation set-up using 2-D Silvaco ATLAS TCAD. With recessed silicon channel, the quantum confinement effects have been considered for channel thickness < 7 nm. In comparison to conventional double gate junctionless FET (C_DGJLFET), the device exhibits lesser OFF-current, improved ON-to-OFF current ratio, better subthreshold slope, and lower drain-induced-barrier-lowering. Analogically, it has been found that the misaligned gate towards drain affects the digital and analog parameters more severely in comparison to gate misalignment towards the source end. However, the misaligned R_DGJLFET towards the drain end shows robustness in terms of subthreshold slope and drain-induced-barrier-lowering with smaller variations of ~10.84% and ~61.79%, respectively. Moreover, due to very low parasitic capacitances, the device shows lesser variations in different AC performance parameters namely, transconductance generation factor, unity gain frequency, and gain-bandwidth product in comparison to C_DGJLFET. With gate misalignment towards source the unity gain frequency, and gain-bandwidth improve by ~9.67% and ~19.9%, respectively whereas the transconductance generation factor remains almost unaffected. Furthermore, to ensure the device capability in circuit application a CMOS inverter and common-source amplifier based on R_DGJLFET have been designed. In contrast to C_DGJLFET based counterpart, the R_DGJLFET expresses its suitability for low-power digital applications with better noise margins and smaller short-circuit current in the CMOS inverter. In analog domain, the R_DGJLFET based common-source amplifier shows an improved amplification factor of 4.75 in comparison to C_DGJLFET. This paper provides deep insight into the severity of gate misalignment towards source/drain for R_DGJLFET in both digital and analog domains from device to circuit level.

Analytical modeling of recessed double gate junctionless field‐effect‐transistor in subthreshold region

“…4 In our previous work, this issue has been addressed with a recently proposed recessed double gate JLFET (R_DGJLFET) which has shown remarkably enhanced performance with improved gate control at both device and circuit levels. [19][20][21] However, the analytical model for R_DGJLFET still needs to be developed to the best of our knowledge. Hence, in this work, we have presented an analytical model used the recently proposed R_DGJLFET operating in the subthreshold region.…”

“…From the literature, it has been concluded that in the sub‐20 nm regime, the performance of JLFETs also starts degrading resulting in increased OFF‐state leakage and SCEs 4 . In our previous work, this issue has been addressed with a recently proposed recessed double gate JLFET (R_DGJLFET) which has shown remarkably enhanced performance with improved gate control at both device and circuit levels 19–21 . However, the analytical model for R_DGJLFET still needs to be developed to the best of our knowledge.…”