Study of electrically active defects in epitaxial layers on silicon

Abstract

Electrically active defects in silicon-based epitaxial layers on silicon substrates have been studied by Deep-Level Transient Spectroscopy (DLTS). Several aspects have been investigated, like, the impact of the pre-epi cleaning conditions and the effect of a post-deposition anneal on the deep-level properties. It is shown that the pre-cleaning thermal budget has a strong influence on the defects at the substrate/epi layer interface. At the same time, a post-deposition Forming Gas Anneal can passivate to a large extent the active defect states. Finally, it is shown that application of a post-deposition anneal increases the out-diffusion of carbon from a Si:C stressor layer into the p-type CZ substrate.

Comparison between Si/SiO2 mid‐gap interface states and deep levels associated with silicon‐oxygen superlattices in p‐type silicon

“…Most DLTS studies on silicon epi layers in the past are concerned with as-deposited n-type silicon [15][16][17], while for p-Si, a band of minority electron traps in the upper half of the bandgap at E C -0.3 eV has been reported, corresponding with the Si-Si interface [18]. This was confirmed on in situ B-doped p + epi layers deposited on n-type Cz Si substrates by CVD [19,20]. The observed majority electron traps have been ascribed to the presence of oxygen and/or carbon at the interface, due to insufficient pre-epi cleaning.…”