Study Of Gate Critical Dimension Uniformity (CDU) Budget and Improvement at 28nm Node

Abstract

Achieving good gate’s critical dimension uniformity (CDU) is very challenging since the CDU has shown not only high sensitivities to the variations in resist track recipe, scanner hardware and control, and etcher condition, but also have high correlation to the feature shape and pattern environment. For process generations at 28 nm half pitch, more aggressive CDU requirement will result in a push of OPC, reticle making and litho process to their limits. To more systematically analyze the linewidth variation and to find a viable solution to achieve required linewidth uniformity, we constructed linewidth variation budget, which includes variations in lithographic process, mask linewidth, optical proximity correction (OPC) error, and scanner control. Through analyzing the CDU requirement from process integration needs and referencing the ITRS roadmap’s recommendation, we have identified key budget contributors, which are OPC and mask making. In this paper, we will demonstrate our achievement in linewidth uniformity improvement.