Study of gate current in advanced MOS architectures

Gauhar, Ghulam Ali; Chenchety, Abhishek; Yenugula, Hashish; Georgiev, Vihar P.; Asenov, A.; Badami, Oves

doi:10.1016/j.sse.2022.108345

Solid-State Electronics

2022

DOI: 10.1016/j.sse.2022.108345

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Study of gate current in advanced MOS architectures

Ghulam Ali Gauhar

Abhishek Chenchety

Hashish Yenugula

et al.

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2024

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Cited by 3 publications

References 10 publications

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Insights into Sub‐Thermionic Transport in Schottky Barrier FETs

Gauhar,

Bhattacharjee,

Badami

2024

Advcd Theory and Sims

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Boltzmann carrier statistics restrict the sub‐threshold swing (SS ≥ 60 mVdec–1) and, consequently, the supply voltage (≈ 1 V) of the thermionic transistor. This primary bottleneck results in rapidly increasing power consumption, heating, and associated reliability/scalability challenges as more devices are packed into a small footprint. Despite significant efforts from the device community, a suitable sub‐thermionic alternative is yet to emerge. In this work, an attempt is made to understand the physics of Schottky barrier FETs demonstrating SS < 60 mVdec–1, as evident in some experimental results. Employing the in‐house TCAD tool, the electrostatic potential in the device is accurately modeled with the sweeping gate bias. Next, the Tsu–Esaki model is used to compute the tunneling current. The analysis shows that the steep SS results from an abrupt change in the tunneling barrier profile, from a step‐like to a triangular‐like. However, in the ON regime, the drift component begins to dominate the transfer characteristics. Thus, the subtle interplay between the drift and tunneling components of transport leads to SS < 60 mVdec–1 in OFF‐state with improved in ON‐state. Finally, using the calibrated model, the performance metrics of an all‐2D material‐based CMOS inverter operating at a low VDD ≈ 0.6 V are projected.

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Insights into Sub‐Thermionic Transport in Schottky Barrier FETs

Gauhar,

Bhattacharjee,

Badami

2024

Advcd Theory and Sims

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A Normalizing Flow Based Validity‐Preserving Inverse‐Design Model for Nanoscale MOSFETs

Ashai,

Badami,

Sarkar

2024

Advcd Theory and Sims

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A two‐stage inverse model for the design of gate‐all‐around nanowire metal oxide semiconductor field effect transistors (MOSFETs) is proposed in this article. The proposed model first validates the selection of output characteristics using a normalizing flow based generative model, and then predicts the device parameters corresponding to the valid output characteristics using a cascade of inverse and forward artificial neural networks (ANNs). This accurately captures any out‐of‐distribution datapoint in the output characteristics distribution and computes the device parameters through the inverse ANN, avoiding any conflicts created by non‐unique mappings. The two‐stage model instantly predicts possible device designs for a target output characteristic set without going for multiple iterations to arrive at a device‐design, highlighting the accuracy and robustness of the model.

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Impact of Process-Induced Inclined Side-Walls on Gate Leakage Current of Nanowire GAA MOSFETs

Maniyar,

Raj,

Srinivas

et al. 2024

IEEE Trans. Electron Devices

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Study of gate current in advanced MOS architectures

Cited by 3 publications

References 10 publications

Insights into Sub‐Thermionic Transport in Schottky Barrier FETs

Insights into Sub‐Thermionic Transport in Schottky Barrier FETs

A Normalizing Flow Based Validity‐Preserving Inverse‐Design Model for Nanoscale MOSFETs

Impact of Process-Induced Inclined Side-Walls on Gate Leakage Current of Nanowire GAA MOSFETs

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