Study of Linearity Performance of Graded Channel Gate Stacks Double Gate MOSFET with Respect to High-K Oxide Thickness

Swain, Sanjit Kumar; Das, Satish Kumar; Adak, Sarosij

doi:10.1007/s12633-019-00257-8

Cited by 11 publications

(4 citation statements)

References 24 publications

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“…Except few there is linearity analysis is one important area because of their dominant role in present RF system needs to study. 42 Our proposed device gives better result in linearity analysis with gate stacking effect. Another some recent literature also gives emphasis on Graded channel and gate stack device for its analog/rf performance analysis, 43,44 in comparison to that our proposed device shows better performance in RF parameters and more linear.…”

Section: Linearity Analysismentioning

confidence: 84%

Study on Analog/RF and Linearity Performance of Staggered Heterojunction Gate Stack Tunnel FET

Biswal¹,

Das²,

Misra³

et al. 2021

ECS J. Solid State Sci. Technol.

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Staggered heterostructure gate stack TFET is proposed. The analog, RF, and linearity performance of the device were studied in an ATLAS TCAD device simulator. The high K material HfO 2 was used in gate stacking. The impact of the gate stack width on the analog, RF, and linearity performance was investigated. Analog/RF performance of the staggered heterostructure gate stack TFET were analyzed in terms of figure of merits (FOMs) like transconductance (g m ), transconductance generation factor (TGF), voltage gain, electric field, cut off frequency (f T ), maximum frequency of oscillation (f max) , and gain band width (GBW). Gate stacking architecture in heterostructure staggered TFET improves the I on /I off ratio and reduces drain induced barrier lowering with respect to greater gate stack width (t oxh ), diminishing the short channel effects. Improvement in g m voltage gain, f T , f max , and GBW) were observed as the gate stack width thickened. A fair comparison of FOMs such as VIP 2 , VIP 3 , IIP 3 , IMD 3 , and 1 dB-compression point (P1 dB) were carried out by varying the gate stack width to investigate the linearity performance. The simulation results reveal that staggered heterostructure gate stack TFET can be a reasonable competitor for low-power applications and in the design of RF circuits covering a wide range in frequencies of RF spectrum.

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Section: Linearity Analysismentioning

confidence: 84%

Study on Analog/RF and Linearity Performance of Staggered Heterojunction Gate Stack Tunnel FET

Biswal¹,

Das²,

Misra³

et al. 2021

ECS J. Solid State Sci. Technol.

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“…Therefore, to overcome the tunneling probability of carriers in SB, the channel‐engineered 26 technique has widely been used in recent years, like asymmetric/graded channel (GC), Dopant Segregation, and non‐uniform doping profiles. These channel‐engineered techniques are a probable solution to the matters associated with SCEs and hot carrier degradation and lead to an immediate increase in transconductance 27–29 . The non‐uniformly doped (NUD) channels have become illuminated among other supporter technology as it increases carrier injection velocity and decreases external resistance 30–32 .…”

Section: Introductionmentioning

confidence: 99%

“…These channelengineered techniques are a probable solution to the matters associated with SCEs and hot carrier degradation and lead to an immediate increase in transconductance. [27][28][29] The non-uniformly doped (NUD) channels have become illuminated among other supporter technology as it increases carrier injection velocity and decreases external resistance. [30][31][32] In the NUD device, an elevated level of doping at the source side progresses the Vth roll-off and overpowers the DIBL.…”

Section: Introductionmentioning

confidence: 99%

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Sharma

Nath

Deswal³

et al. 2023

Int J Numerical Modelling

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This study's objectives are to deliver a relative analysis of non‐uniformly doped (NUD) and uniformly doped Dual Metal High‐K Schottky nanowire FET (DM‐HK‐SNWFET). Surface potential, subthreshold current, subthreshold swing, and drain current have been expressed and analyzed by resolving 2D Poisson's equation with suitable boundary conditions. The analog performance of the device is verified by examining cut‐off frequency (fT), trans‐conductance frequency product (TFP), gain frequency product (GFP), and gain trans‐conductance frequency product (GTFP). The results show suitable RF circuit parameters with a high switching ratio (≈3 × 109) and low subthreshold swing (61 mV/decade) for NUD‐DM‐HK‐SNWFET. Additionally, linearity frequency of merits (FOMs) and distortion performance are also studied by numerically calculating higher order voltage and current intercept point (VIP2, VIP3, IIP3, IMD3); 1‐dB compression point and Harmonics distortions (HD2 and HD3) using transconductance (gm1) along with its higher derivatives gm2 and gm3. These parameters exhibit high‐level linearity and low‐level distortion at zero crossover points in NUD‐DM‐HK‐SNWFET, making it a better contender for low‐power and high‐performance applications.

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“…Multiple methodologies are incorporated in conventional MOSFETs to improve the performance at nanoscale, which are namely reduction in gate oxide thickness, increased doping concentration, indulging high-k dielectrics, incorporation of dual material gate, pocket implantation, lateral channel engineering, silicon-on-insulator (SOI) technology, strained silicon (s-Si) technology [4][5][6][7][8]. But, as source and drain doping concentrations are increased the mobility of charge carriers decreases, while the junction capacitances at gate-source (Cgs) and at gate-drain (Cgd) escalate significantly [3,[5][6][7][8][9]. With reduction in gate oxide thickness the carriers acquire enough energy due to applied gate voltage and become trapped into the gate oxide region at high electric field [10].…”

Section: Introductionmentioning

confidence: 99%

Physics and Modelling of Tri-Layered Strained Channel for Development of Double Gate n-channel FET

Kumar

Dhar

2021

Preprint

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The strain silicon technology with FET is a dominant technology providing enrichment in carrier velocity in nanoscaled device by change of band structure arrangement. Leakage reduction while enhancement in drain current is another major objective therefore, designing a nano-regime double gate FET with strained channel is perceived. So, design and implementation of a double gate strained heterostructure on insulator (DG-SHOI) FET with tri-layered channel (s-Si/s-SiGe/s-Si) is the core. Biaxial strain is created in channel by inculcating three layers with optimal thicknesses while narrow channel depletion regions are strongly controlled by equipotential gates. Consequently, maximum charge carriers accumulate in channel due to quantum carrier confinement instigating ballistic transport across the 22 nm channel length device leading to lessening of intervalley scattering. In comparison to existing 22 nm DGSOI FET, drain current augmentation of 56% and transconductance amplification of 87.6% is observed while DIBL is prudently reduced for this newly designed and implemented DG-SHOI FET, signifying advancement in microelectronic technology.

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Study of Linearity Performance of Graded Channel Gate Stacks Double Gate MOSFET with Respect to High-K Oxide Thickness

Cited by 11 publications

References 24 publications

Study on Analog/RF and Linearity Performance of Staggered Heterojunction Gate Stack Tunnel FET

Study on Analog/RF and Linearity Performance of Staggered Heterojunction Gate Stack Tunnel FET

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Physics and Modelling of Tri-Layered Strained Channel for Development of Double Gate n-channel FET

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