Study of low frequency noise in the 0.18 μm silicon CMOS transistors

Boutchacha, T.; Ghibaudo, G.; Belmekki, B.

doi:10.1109/icmts.1999.766221

Cited by 14 publications

(17 citation statements)

References 20 publications

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“…Additionally, recent measurements show higher values of flicker-noise factors in newer processes, likely due to increased processing damage at the Si-SiO 2 interface. Finally, the data given in [57,96] shows that gate-referred, flicker-noise voltage increases modestly for nMOS devices, but increases significantly for pMOS devices for operation at high V GS −V T in strong inversion. Such bias-related increases, however, can likely be managed by operation in moderate inversion or near the onset of strong inversion (IC = 10, V GS −V T ≈ 0.225 V) as required for low V GS −V T and V DSAT in low-voltage designs.…”

Section: Flicker Noisementioning

confidence: 94%

“…Flicker-noise factors for operation near the onset of strong inversion (V GS − V T = 0.2 V) are higher at 10.6 × 10 −31 and 18.8×10 −31 C 2 /cm 2 for nMOS and pMOS devices in a 0.18-µm process having gate-oxide thickness of 4.5 nm [96]. Values for operation in strong inversion at V GS − V T = 0.5 V are even higher at 26 × 10 −31 C 2 /cm 2 for both nMOS and pMOS devices in a nitrided process having gate-oxide thickness of 4 nm [100].…”

Section: Flicker Noisementioning

confidence: 97%

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Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

Binkley

Blalock

Rochelle³

2006

Analog Integr Circ Sig Process

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This paper describes a methodology for selecting drain current, inversion level (represented by inversion coefficient), and channel length for optimum performance tradeoffs in analog CMOS design. Here, inversion coefficient replaces width as a design choice to permit a conscious optimization of inversion level while width is implicitly considered. Transconductance, gate-referred thermal-noise voltage, and drain-source saturation voltage are optimized towards weak inversion while transconductance linearity and drain-referred thermal-noise current are optimized in strong inversion. Voltage gain, flicker noise, and dc mismatch are optimized towards weak inversion at long channel length while bandwidth is optimized in strong inversion at short channel length. Optimization expressions are given along with measured transconductance efficiency and Early voltage from weak through strong inversion over a wide range of channel lengths. Transconductance efficiency and Early voltage are used as normalized measures of transconductance and drain-source resistance, independent of drain current. The methodology presented is used to design three 0.5-µm operational transconductance amplifiers having equal 50-µA bias currents, but different tradeoffs in gain, bandwidth, noise, and dc mismatch. The amplifiers have measured voltage gains of 16.8, 110, and 326 V/V, −3-dB bandwidths of 350, 51, and 5 MHz, input-referred flicker-noise voltage at 100 Hz of 2,000, 450, and 58 nV/Hz 1/2 , and input-referred dc mismatch voltages of 10.2, 2.2, and 1.1 mV respectively. The design methodology can be readily extended to deeper submicron CMOS processes.

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Section: Flicker Noisementioning

confidence: 94%

Section: Flicker Noisementioning

confidence: 97%

Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

Binkley

Blalock

Rochelle³

2006

Analog Integr Circ Sig Process

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“…From the observed discrepancy S vfb (f) and α S can be deduced [9]. The variations of S vfb (f) versus (W.L) and of S α versus L are reported in figure 4.…”

Section: Experimental Data and Modellingmentioning

confidence: 97%

1/f Noise Modeling in a-Si TFTs by BSIM Software

Rhayem

Rigaud²,

Contaret³

et al. 2000

30th European Solid-State Device Research Conference

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1/f noise has been studied in amorphous silicon inverted staggered thin film transistors over different gate geometries. It is shown that the origin of this noise changes when the gate area is scaled down. For large gate geometries mobility fluctuations (Hooge model) prevail whereas for small gate dimensions correlated number-mobility fluctuations (∆N-∆µ model) are involved. In any case, we have used BSIM to obtain 1/f noise modeling. It is pointed out some terms in order to obtain simulation accuracy. Good agreement is observed showing BSIM possibilities to model excess noise in thin film devices.

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“…13 for Si and SiGe channels. As can be seen, the LF noise can be well attributed to the carrier number fluctuation with correlated mobility fluctuations as given by following equation [21]:…”

Section: Low Frequency Noisementioning

confidence: 98%