Study of mechanism of stress-induced threshold voltage shift and recovery in top-gate amorphous-InGaZnO4 thin-film transistors with source- and drain-offsets

Mativenga, Mallory; Kang, Da Hyun; Lee, Ung Gi; Jang, Jin

doi:10.1016/j.ssc.2012.06.012

Cited by 14 publications

(6 citation statements)

References 16 publications

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“…For a-IGZO TFTs, the results for bias-dependent I – V characteristics suggested that ionized O vacancy defects migrate at room temperature [19]. Recently, the suppression of NBIS degradation was observed under a large drain voltage, which can be explained by drift and accumulation of ionized O vacancies in the drain region [46].…”

Section: Drift Motion Of the Ionized O Vacancy Under An Electric Fieldmentioning

confidence: 99%

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The effects of electric field and gate bias pulse on the migration and stability of ionized oxygen vacancies in amorphous In–Ga–Zn–O thin film transistors

Noh

Chang

2015

Science and Technology of Advanced Materials

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Oxygen vacancies have been considered as the origin of threshold voltage instability under negative bias illumination stress in amorphous oxide thin film transistors. Here we report the results of first-principles molecular dynamics simulations for the drift motion of oxygen vacancies. We show that oxygen vacancies, which are initially ionized by trapping photoexcited hole carriers, can easily migrate under an external electric field. Thus, accumulated hole traps near the channel/dielectric interface cause negative shift of the threshold voltage, supporting the oxygen vacancy model. In addition, we find that ionized oxygen vacancies easily recover their neutral defect configurations by capturing electrons when the Fermi level increases. Our results are in good agreement with the experimental observation that applying a positive gate bias pulse of short duration eliminates hole traps and thus leads to the recovery of device stability from persistent photoconductivity.

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Section: Drift Motion Of the Ionized O Vacancy Under An Electric Fieldmentioning

confidence: 99%

“…From field-dependent I – V characteristics of a-IGZO TFTs, it was inferred that ionized defects easily migrate at room temperature, thus supporting the O vacancy model [19]. However, the details of O vacancy migration during device operation are not well understood.…”

Section: Introductionmentioning

confidence: 99%

The effects of electric field and gate bias pulse on the migration and stability of ionized oxygen vacancies in amorphous In–Ga–Zn–O thin film transistors

Noh

Chang

2015

Science and Technology of Advanced Materials

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“…22 These AOSs can include ZnO, InZnO (IZO), ZnSnO (ZTO), InSnZnO (ITZO), and InGaZnO (IGZO). 5,6,10,19,[22][23][24][25][26][27][28] The major advantage of AOSs against other conventional semiconductors is the room temperature deposition applicability. 29 Specifically, IGZO demonstrated a very high performance as an active layer in TFT, due to its large on/off current ratio, high field effect mobility, low threshold voltage, and sharp sub threshold swing.…”

Section: Introductionmentioning

confidence: 99%

Simulating the I‐V characteristics of an ultrathin IGZO‐based thin film transistor using finite element method

Hussien

Abdellatif

2021

Int J Numerical Modelling

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Thin film transistors (TFTs) are ranked as one of the promising field-effect transistors in the electronic industry. TFTs showed a great potential in many applications where liquid crystal displays, touchscreens, and biosensors are of the leading. In the current study, we are demonstrating a numerical carrier transport model based on finite element method (FEM), to investigate InGaZnO (IGZO) based TFTs. Amorphous silicon TFT has been simulated as a bare device. The impact of scaling down the dimension of the TFT, up to 30 nm channel length, on the output performance characteristics of the transistor has been addressed. Additionally, the effects of active semiconductor layer doping concentration and oxide layer thickness have been investigated. Moreover, a novel approach is introduced to correlate the selected input design parameters with a set of characteristic outputs including threshold voltage, on/off current ratio, and subthreshold swing. The proposed model correlates input and outputs using a characteristic matrix with nine coefficients, making it possible to predict, that is, interpolate, the characteristic outputs within the system boundaries. The suggested model was verified with respect to input data as well as data from the literature showing a very acceptable agreement.

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“…However, these mechanisms are valid for a-IGZO TFTs without source and drain-offsets, such as the conventional bottom-gate inverted-staggered structures. Mativenga et al [13] showed the reason why the gate dielectric SiO 2 layer is applied to the various gate bias-stresses (V G_STRESS ) of the top-gate structure and why the bias voltage (bias stress) is used in detail. The migration of positive charges towards the offsets lowers the local resistance of the offsets, resulting in an abnormal negative V th under positive V G_STRESS .…”

Section: Introductionmentioning

confidence: 99%

Electrical Characteristics and Stability Improvement of Top-Gate In-Ga-Zn-O Thin-Film Transistors with Al2O3/TEOS Oxide Gate Dielectrics

et al. 2020

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In this work, two stacked gate dielectrics of Al2O3/tetraethyl-orthosilicate (TEOS) oxide were deposited by using the equivalent capacitance with 100-nm thick TEOS oxide on the patterned InGaZnO layers to evaluate the electrical characteristics and stability improvement of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) devices, including positive bias stress (PBS) and negative bias stress (NBS) tests. Three different kinds of gate dielectrics (Al2O3, TEOS, Al2O3/TEOS) were used to fabricate four types of devices, differing by the gate dielectric, as well as its thickness. As the Al2O3 thickness of Al2O3/TEOS oxide dielectric stacks increased, both the on-current and off-current decreased, and the transfer curves shifted to larger voltages. The lowest ∆Vth of 0.68 V and ∆S.S. of −0.03 V/decade from hysteresis characteristics indicate that the increase of interface traps and charge trapping between the IGZO channel and gate dielectrics is effectively inhibited by using two stacked dielectrics with 10-nm thick Al2O3 and 96-nm thick TEOS oxide. The lowest ∆Vth and ∆S.S. values of a-IGZO TFTs with 10-nm thick Al2O3 and 96-nm thick TEOS oxide gate dielectrics according to the PBS and NBS tests were shown to have the best electrical stability in comparison to those with the Al2O3 or TEOS oxide single-layer dielectrics.

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Study of mechanism of stress-induced threshold voltage shift and recovery in top-gate amorphous-InGaZnO4 thin-film transistors with source- and drain-offsets

Cited by 14 publications

References 16 publications

The effects of electric field and gate bias pulse on the migration and stability of ionized oxygen vacancies in amorphous In–Ga–Zn–O thin film transistors

The effects of electric field and gate bias pulse on the migration and stability of ionized oxygen vacancies in amorphous In–Ga–Zn–O thin film transistors

Simulating the I‐V characteristics of an ultrathin IGZO‐based thin film transistor using finite element method

Electrical Characteristics and Stability Improvement of Top-Gate In-Ga-Zn-O Thin-Film Transistors with Al2O3/TEOS Oxide Gate Dielectrics

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