Study of Plasma Arcing Mechanism in High Aspect Ratio Slit Trench Etching

Chung, Yen; Lung, Cheng-Yi; Chiu, Yuan-Chieh; Lee, Hong-Ji; Lian, Nan-Tzu; Yang, Tahone; Chen, Kuang-Chao; Lu, Chih‐Yuan

doi:10.1109/asmc.2019.8791770

Cited by 10 publications

(3 citation statements)

References 4 publications

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“…Depending on the etch chemistry, high polymerization can result in sidewall tapering and prevent etch completion to the target depth. A key challenge of channel etching is to achieve appropriate polymerization, so the etch reaches the bottom contact without delivering excessive lateral etch bias at the top of the channel 34 , 35 . Quantifying the extent of hole CD variation and channel taper from the top of the channel to the bottom can be achieved with virtual process modeling and metrology as shown in Fig.…”

Section: D Nandmentioning

confidence: 99%

Review of virtual wafer process modeling and metrology for advanced technology development

Hargrove

Wen

Yim

et al. 2023

J. Micro/Nanopattern. Mats. Metro.

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Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development is a major contributor to time and cost overruns. The growing inability to characterize many of the subtle and complicated features and yield limiting factors of a given technology is another serious constraint. We demonstrate the use of process modeling, virtual wafer fabrication, and virtual metrology in process development of advanced logic and memory. Accurate and predictive process modeling, in combination with virtual metrology enables the characterization of any feature on any given structure, is becoming a key requirement in advanced technology development. Virtual fabrication also accelerates the semiconductor development cycle, by substituting limited and lengthy wafer-based experiments with fast, large-scale virtual design of experiment. Several applications of virtual process modeling and metrology are illustrated in 3D NAND, DRAM, and logic technology. These applications include studies of 3D NAND pillar etch alignment (including tilt, twist, and bowing), DRAM capacitor process window optimization, advanced FinFET logic pitch-walking, and BEOL performance optimization.

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Section: D Nandmentioning

confidence: 99%

Review of virtual wafer process modeling and metrology for advanced technology development

Hargrove

Wen

Yim

et al. 2023

J. Micro/Nanopattern. Mats. Metro.

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show abstract

“…The narrower margins inherent in the programmed V TH distribution of multilevel cells introduce novel complexities and potential issues, diverging from the relative simplicity of single-level cells (SLCs) [13]. Incorporating the HAR structure into 3D NAND introduces a notable rise in process complexity, which, in turn, influences electrical performance and reliability [14][15][16][17]. This technology relies on the utilization of multiple stacked control gates and insulators crafted from alternating thin films of metal and silicon dioxide (SiO 2 ).…”

Section: Introductionmentioning

confidence: 99%

Effect of Noncircular Channel on Distribution of Threshold Voltage in 3D NAND Flash Memory

Go,

Yoon,

Park

et al. 2023

Micromachines

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The instability in threshold voltage (VTH) and charge distributions in noncircular cells of three-dimensional (3D) NAND flash memory are investigated. Using TCAD simulation, we aim to identify the main factors influencing the VTH of noncircular cells. The key focus is on the nonuniform trapped electron density in the charge trapping layer (CTL) caused by the change in electric field between the circular region and the spike region. There are less-trapped electron (LT) regions within the CTL of programmed noncircular cells, which significantly enhances current flow. Remarkably, more than 50% of the total current flows through these LT regions when the spike size reaches 15 nm. We also performed a comprehensive analysis of the relationship between charge distribution and VTH in two-spike cells with different heights (HSpike) and angles between spikes (θ). The results of this study demonstrate the potential to improve the reliability of next-generation 3D NAND flash memory.

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“…In particular, in semiconductor fabrication, plasmas significantly influence the plasma etching [ 4 , 5 , 6 , 7 ], ashing [ 8 , 9 ], and deposition [ 10 , 11 ] processes to realize feature sizes on the nanoscale. As feature sizes continue to shrink towards a few nanometers with improved levels of integration, process abnormalities such as arcing and leakage that reduce productivity have been regarded as serious problems [ 12 , 13 , 14 ].…”

Section: Introductionmentioning

confidence: 99%

Development of a High-Linearity Voltage and Current Probe with a Floating Toroidal Coil: Principle, Demonstration, Design Optimization, and Evaluation

Kim

Seong

Lee

et al. 2022

Sensors

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As the conventional voltage and current (VI) probes widely used in plasma diagnostics have separate voltage and current sensors, crosstalk between the sensors leads to degradation of measurement linearity, which is related to practical accuracy. Here, we propose a VI probe with a floating toroidal coil that plays both roles of a voltage and current sensor and is thus free from crosstalk. The operation principle and optimization conditions of the VI probe are demonstrated and established via three-dimensional electromagnetic wave simulation. Based on the optimization results, the proposed VI probe is fabricated and calibrated for the root-mean-square (RMS) voltage and current with a high-voltage probe and a vector network analyzer. Then, it is evaluated through a comparison with a commercial VI probe, with the results demonstrating that the fabricated VI probe achieved a slightly higher linearity than the commercial probe: R2 of 0.9967 and 0.9938 for RMS voltage and current, respectively. The proposed VI probe is believed to be applicable to plasma diagnostics as well as process monitoring with higher accuracy.

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Study of Plasma Arcing Mechanism in High Aspect Ratio Slit Trench Etching

Cited by 10 publications

References 4 publications

Review of virtual wafer process modeling and metrology for advanced technology development

Review of virtual wafer process modeling and metrology for advanced technology development

Effect of Noncircular Channel on Distribution of Threshold Voltage in 3D NAND Flash Memory

Development of a High-Linearity Voltage and Current Probe with a Floating Toroidal Coil: Principle, Demonstration, Design Optimization, and Evaluation

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