Study of pore structure and stability in porous low-k interconnects using electrolyte voltammetry

Meng, Dong Mei; Michael, N. L.; Kim, Choong Un; Park, Young Joon

doi:10.1063/1.2218060

Cited by 7 publications

(5 citation statements)

References 9 publications

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“…Most are based on forming an interface between Cu and the barrier material and using techniques such as secondary ion mass spectroscopy (SIMS) or Rutherford backscattering to monitor for Cu in-diffusion into the barrier and ILD material, 265,266 or X-ray diffraction to detect Cu diffusion into the underlying Si substrate and formation of CuSi x . 267,268 Various electrical [269][270][271][272][273] and electrochemical 274,275 tests have also been reported in the literature for evaluating the Cu diffusion resistance of barrier materials. Based on these various methods, PECVD a-SiN:H has been shown to be an excellent Cu diffusion barrier.…”

Section: -122mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

133

115

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Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore's law (i.e. More Moore) and More than Moore scaling.

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Section: -122mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

133

115

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“…12,13,21 The introduction of nano-porosity has also been noted to degrade the electrical properties of low-k materials including increased leakage currents, decreased breakdown voltages (V bd ), and shortened times for time dependent dielectric breakdown failures (TDDB). [22][23][24][25] The introduction of nano-porosity also allows for the increased diffusion of ambient moisture, 8,9,26,27 wet chemicals, 28,29 Cu, 11,30,31 and other metallic/ionic species [32][33][34] through low-k materials both during processing and in operation. This is a particularly troublesome problem for the Cu capping/etch stop layer as it additionally serves as a diffusion barrier for both out diffusion of Cu, 6,35 in diffusion of moisture, 8,9 and in diffusion of wet chemicals utilized in next layer processing (primarily post patterning 36,37 and post CMP cleans [38][39][40] ).…”

mentioning

confidence: 99%

Film Property Requirements for Hermetic Low-k a-SiO_xC_yN_z:H Dielectric Barriers

King

Jacob

Vanleuven

et al. 2012

ECS J. Solid State Sci. Technol.

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Continued reduction in resistance-capacitance (RC) delays in nano-electronic Cu interconnect structures will require new materials with increasingly lower dielectric constants (i.e. low-k). Significant reductions in RC delay can be achieved by reducing the dielectric constant of the relatively high dielectric constant Cu capping/etch stop layer. However, this risks comprising the required barrier performance of this material to the diffusion of Cu, H 2 O, and other species. In this regard, critical thresholds for the diffusion of water and solvents through low-k a-SiO x C y N z :H dielectrics of varying composition were investigated using a combination of X-ray reflectivity mass density and positronium annihilation lifetime spectroscopy pore size metrologies. It was observed that hermetic low-k a-SiO x C y N z :H dielectrics were achieved only at mass densities >2.0 g/cm 3 and when the pore diameter was less than twice the molecular diameter of water. The implications of these critical nano-porosity thresholds on continued scaling of low-k diffusion barrier and ILD materials are discussed as well as methods for overcoming these limitations.

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“…Since the kinetics of the decaying current are not affected by external field (no external field exists) and governed only by internal diffusion, diffusivity can be computed based on Fickian diffusion model. Then, the pore structure can be indirectly characterized from the ion diffusivity using its sensitivity to pore size and porosity, as is presented elsewhere [13].…”

Section: Discussionmentioning

confidence: 99%

Development of Voltammetry-Based Techniques for Characterization of Porous Low-k/Cu Interconnect Integration Reliability

Kim¹,

Chen

Michael

et al. 2011

ECS Trans.

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This paper concerns the new method of detecting the integration failures in porous low-k (PLK)/Cu interconnects using simple voltammetry-based techniques. In essence, the technique takes advantage of the fact that pores in PLK allow permeation of liquid, including electrolyte, into interconnect structures. The infiltration of electrolyte allows the formation of a micro-cell, consisting of two mating Cu interconnect electrodes and the electrolyte in PLK, where simple linear voltammetry can examine various integration reliability issues pertinent to PLK/Cu interconnects. Specifically, the technique is proven to be effective in detection of 1) failure in Ta barrier, 2) cracks in the capping layer, and 3) trapped impurity in pores in PLK. The working principle of the voltammetry technique and demonstration of its effectiveness is introduced in this paper.

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Study of pore structure and stability in porous low-k interconnects using electrolyte voltammetry

Cited by 7 publications

References 9 publications

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Film Property Requirements for Hermetic Low-k a-SiO_xC_yN_z:H Dielectric Barriers

Development of Voltammetry-Based Techniques for Characterization of Porous Low-k/Cu Interconnect Integration Reliability

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Study of pore structure and stability in porous low-k interconnects using electrolyte voltammetry

Cited by 7 publications

References 9 publications

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Film Property Requirements for Hermetic Low-k a-SiOxCyNz:H Dielectric Barriers

Development of Voltammetry-Based Techniques for Characterization of Porous Low-k/Cu Interconnect Integration Reliability

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Film Property Requirements for Hermetic Low-k a-SiO_xC_yN_z:H Dielectric Barriers