Study of selective isotropic etching Si1−xGex in process of nanowire transistors

Li, Junjie; Wang, Wenwu; Li, Yongliang; Zhou, Na; Wang, Guilei; Kong, Zhenzhen; Fu, Jianyu; Yin, Xiaogen; Li, Chen; Wang, Xiaolei; Yang, Hong; Ma, Xueli; Han, Jing; Zhang, Jing; Wei, Yijun; Hu, Tairan; Yang, Tao; Li, Junfeng; Zhu, Huilong; Radamson, Henry H.

doi:10.1007/s10854-019-02269-x

Cited by 26 publications

(37 citation statements)

References 24 publications

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“…However, using CF 4 /O 2/ He in traditional inductively coupled plasma (ICP) for SiGe selective etching has achieved a good etching effect. The etching morphology has advantages over wet etching as shown in Figure 34 and damaged material can be removed and the SiGe layer is preserved as shown in high-reosultion reciprocal lattice maps (HRRLMs) in Figure 35 [ 207 ]. The position of SiGe peak in all maps is aligned to the Si peak imdicating neglible strain relaxation after initial vertical etch and in consequence of lateral etch steps.…”

Section: Advanced Etching For Nano-transistor Structuresmentioning

confidence: 99%

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State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Section: Advanced Etching For Nano-transistor Structuresmentioning

confidence: 99%

“… The SEM images of cross section comparing the profile between wet etching and inductively coupled plasma (ICP) dry etching: ( a ) Wet etching SiGe with 6% HF/30% H 2 O 2/ 99.8% CH 3 COOH = 1:2:4 etching 8 min, and ( b ) ICP dry etching SiGe with CF 4 /O 2 /He = 4:1:5 [ 207 ]. …”

Section: Figurementioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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“…Step 2: 3 µm equally spaced line arrays were patterned, and the whole structure including the hard mask and Si 0.72 Ge 0.28 /Si stack are vertically etched to the substrate silicon by using the plasma etching. Finally, oxygen plasma is used to remove the photoresist [15].…”

Section: Effect Of Thin Film Process On Gap Fillingmentioning

confidence: 99%

“…Step 3: In the ICP etching tool, the Si 0.72 Ge 0.28 layers were selectively etched by CF 4 /O 2 /He gas without any bias power, to obtain the lateral depth of 50-70 nm [15].…”

Section: Effect Of Thin Film Process On Gap Fillingmentioning

confidence: 99%

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

Zhou

et al. 2020

Nanomaterials

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Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

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“…In our previous work, the new CF 4 /O 2 /He reaction system without bias power plasma etching technology was studied, but its etching accuracy still needs to be improved because of its continuous etching characteristics [32]. Then, the method of H 2 O 2 and BOE alternate cycle self-selective etching of SiGe was studied, and the etching accuracy was remarkably improved.…”

Section: Introductionmentioning

confidence: 99%

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm

Zhou

et al. 2020

Materials

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Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.

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Study of selective isotropic etching Si1−xGex in process of nanowire transistors

Cited by 26 publications

References 24 publications

State of the Art and Future Perspectives in Advanced CMOS Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm

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