Study of SEU effects in circuits developed in 110 nm CMOS technology

Abstract

Channel configuration registers of a full size prototype for the custom readout circuit of silicon double-sided microstrips of PANDA Micro Vertex Detector were tested for upset effects. The ASIC is developed in a commercial 110 nm CMOS technology and implements both Triple Modular Redundancy and Hamming Encoding techniques. Results from tests with ion and proton beams show the robustness level of these two techniques against the upset effects and allow the evaluation of that commercial 110 nm technology in the PANDA experiment.

FAIR status and the PANDA experiment

“…Closest to the interaction point a silicon based tracker, the Micro Vertex Detector (MVD) [49] is planned to provide vertex resolutions of about 50 µm in transverse and 100 µm along the beam direction. Pixel sensors, at the inner most layers and double-sided strips sensors will use ASICs developed in PANDA [50] with radiation hard front-end readout and power drivers developed at CERN [51,52]. Surrounding the MVD, the Straw Tube Tracker (STT) and Gas Electron Multiplier (GEM) stations will be used for tracking charged particles with a transverse momentum resolution of about 1.2% in the magnetic field.…”