Study of the pattern aware OPC

Abstract

It's critical to address the yield issues caused by process specific layout patterns with limited process window. RETs such as PWOPC are introduced to guarantee high lithographic margin, but these techniques cost high run-time when applied to full-chips. There's also lack of integrated solution to easily identify, define comprehensive patterns and apply different controls and/or constraints over these patterns through different stages of OPC/RET process.In this paper, we study a pattern aware OPC flow that applies PWOPC or specific corrections locally to layouts with critical and yield limiting patterns. Although the full chip PWOPC provides an effective way, it causes great amount of run time penalty and does not achieve optimal process window. Overall, PAOPC achieves the better margins over the hotspots, without sacrificing turnaround time. The study demonstrates the benefit of the new flow with fine grained process window controls over different patterns. This flow get good improvement on defect counts when evaluated on 50 nm node logic devices.

Cascadic multigrid algorithm for robust inverse mask synthesis in optical lithography

“…[1][2][3] Inverse lithography technology (ILT), 4,5 as an active approach of RETs, is considered as an effective and economically viable way to meet various challenges in current and future technology nodes. 6,7 To put ILT into practice, various methods have been proposed by academic as well as industrial communities on mask manufacturing rule constraints, 8,9 pattern grouping strategy to accelerate computing, 10 GPU-based hardware accelerated techniques, 11 and mathematical solution methods for the inverse problem. 4,5 In this paper, we focus on improvement of mathematical solution methods, where the computational efficiency is one of the most noteworthy issues.…”