Study of Thermo-Mechanical Reliability of TSV for 8-Layer Stacked Multi Chip Package

Abstract

Through silicon via (TSV) technology is becoming a hot topic for three dimensional integration in IC packaging industry. However, TSV technology raises several reliability concerns particularly caused by thermally induced stress. In this study, the thermo-mechanical reliability of copper TSV technology for the multi chip packaging was investigated using finite element method. For the multi chip package design, the 8-layer stacked chip packaging with TSV structure has been constructed as our test vehicle. The numerical analysis of stress/strain distribution and thermal fatigue life prediction were performed in order to study the impact of several design parameters such as via diameter, via pitch, die thickness, bonding pad geometry. The effects of various underfill materials which have different Young¡¯s modulus and coefficients of thermal expansion (CTEs) were also investigated. The DOE (design of experiment) analysis was performed to find the optimal design conditions for 8-layer multi chip package. The most influential factors for the stress reduction are TSV diameter and the coefficient of thermal expansion of underfill material. The larger via diameter and lower CTE showed the smaller stress distribution. On the other hand, thermal fatigue life increases with via diameter, and becomes maximum at via diameter of 20 um, then decrease with increasing via diameter. The presence of underfill material significantly increased the thermal fatigue life of TSV structure. The bonding pad design is also important for TSV durability. The smaller bonding pad showed less stress and higher thermal fatigue life. The characteristics of warpage for 8-layer multi chip package were also investigated.