Study of Vertical Capacitance in an n-Type 4H-SiC Stepped Thick-Oxide Trench MOS Structure

Guo, Zhiyu; He, Zhi; Wang, Fengxuan; Wu, Jincheng; Yang, Xiang; Fan, Zhiqin; Fh, Yang

doi:10.1109/ted.2022.3179995

Cited by 5 publications

(3 citation statements)

References 35 publications

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“…The ALD 20c sample was observed to have the minimal EOT, indicating the best interfacial chemistry, which was attributed to the growth inhibition of the ErSmO/InP capacitor interface by the high-quality gate dielectric and the passivation layer Al 2 O 3 with appropriate growth cycles. Further, the origin of negative Q ox could be the presence of massive shallow states in the oxide near the interface, where the shallow states trap electrons, resulting in a complete compensation of the positive charge presented in the oxide layer . The Q ox of all samples remained at the same level and showed no obvious difference, indicating that the interfacial shallow state content is not much different.…”

Section: Resultsmentioning

confidence: 95%

“…Further, the origin of negative Q ox could be the presence of massive shallow states in the oxide near the interface, where the shallow states trap electrons, resulting in a complete compensation of the positive charge presented in the oxide layer. 45 The Q ox of all samples remained at the same level and showed no obvious difference, indicating that the interfacial shallow state content is not much different.…”

Section: Electrical Performance Analyses Of Inp-mos Capacitors 331 C−...mentioning

confidence: 86%

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Interface Chemistry and Defect State Optimization of the ErSmO/InP Heterojunction Modified by ALD-Driven Al₂O₃ Interlayers

Lü

Wang

et al. 2023

ACS Appl. Electron. Mater.

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In this work, the effects of the atomic-layer deposition (ALD)-derived Al2O3 passivation layer with different growth cycles on the interfacial chemistry and electrical performance of sputtering-driven ErSmO/InP metal oxide semiconductor (MOS) capacitors have been comparatively investigated. Atomic force microscopy (AFM) and X-ray photoelectron spectroscopy (XPS) characterization have confirmed that the ALD-driven Al2O3 passivation layer with 20 growth cycles could form a flat dielectric layer and effectively suppress the diffusion of In and P elements at the InP interface. Meanwhile, the ErSmO/Al2O3/InP gate stack with 20 growth cycles exhibited optimal electrical properties, including a large dielectric constant of 37.42, a minimum interface state density (D it) of 5.43 × 1011 eV–1 cm–2, and a low leakage current of 3.95 × 10–6 A/cm–2. The leakage current conduction mechanisms of InP-MOS capacitors measured at room temperature and low temperature have also been systematically analyzed. Particularly, low-frequency noise (LFN) is used to evaluate trap levels in InP-MOS capacitors. All experimental results have demonstrated that the ErSmO/Al2O3/InP gate stack has potential applications in future ultrahigh-speed and high-frequency microelectronic devices.

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Section: Resultsmentioning

confidence: 95%

Section: Electrical Performance Analyses Of Inp-mos Capacitors 331 C−...mentioning

confidence: 86%

Interface Chemistry and Defect State Optimization of the ErSmO/InP Heterojunction Modified by ALD-Driven Al₂O₃ Interlayers

Lü

Wang

et al. 2023

ACS Appl. Electron. Mater.

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“…In order to increase the device switching and gate control over the channel, space is added between the two gates. [ 14–16 ] 2D device simulation is done and the DSGT and m‐DSGT device is compared with the conventional VDMOS. The outcomes are investigated and enhanced linearity, decreased switching delay, reduction in specific on‐resistance (

$R_{\text{on}} .

…”

Section: Introductionmentioning

confidence: 99%

Dual‐Stepped Gate Vertical Double‐Diffused Metal‐Oxide‐Semiconductor Field‐Effect Transistor with Enhanced Device Performance

Sidar,

Parmar,

Mishra

2024

Physica Status Solidi (a)

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In this paper, Vertical Double Diffused MOSFET(VDMOS) with improved device structure is proposed. Gate engineering is applied in the proposed device and two devices namely dual stepped gate technology(DSGT) and modified dual stepped gate technology(m‐DSGT) are proposed here. Due to the effect of gate engineering switching ability is improved and area specific ON‐resistance is reduced. Devices are simulated using Silvaco Atlas software. Breakdown voltages for conventional and m‐DSGT are 278.63V and 280.02V, respectively, for VGS=0V. The current density of conventional and m‐DSGT devices is 49.2A/cm2 and 178.5A/cm2 under the conditions on gate drive voltage of 1V for VDS=10V. Using 2‐D numerical simulations, the electrical performance of both DSGT and m‐DSGT devices is examined. The results demonstrate 76.6% decrease in specific ON‐resistance, 4.22 times increase in current density and 26.67% faster switching speed compared to conventional VDMOS. Thus, improving the device performance.This article is protected by copyright. All rights reserved.

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A 4H-SiC Trench MOS Capacitor Structure for Sidewall Oxide Characteristics Measurement

Huang,

Hsuesh,

et al. 2024

2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS)

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Study of Vertical Capacitance in an n-Type 4H-SiC Stepped Thick-Oxide Trench MOS Structure

Cited by 5 publications

References 35 publications

Interface Chemistry and Defect State Optimization of the ErSmO/InP Heterojunction Modified by ALD-Driven Al₂O₃ Interlayers

Interface Chemistry and Defect State Optimization of the ErSmO/InP Heterojunction Modified by ALD-Driven Al₂O₃ Interlayers

Dual‐Stepped Gate Vertical Double‐Diffused Metal‐Oxide‐Semiconductor Field‐Effect Transistor with Enhanced Device Performance

A 4H-SiC Trench MOS Capacitor Structure for Sidewall Oxide Characteristics Measurement

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Study of Vertical Capacitance in an n-Type 4H-SiC Stepped Thick-Oxide Trench MOS Structure

Cited by 5 publications

References 35 publications

Interface Chemistry and Defect State Optimization of the ErSmO/InP Heterojunction Modified by ALD-Driven Al2O3 Interlayers

Interface Chemistry and Defect State Optimization of the ErSmO/InP Heterojunction Modified by ALD-Driven Al2O3 Interlayers

Dual‐Stepped Gate Vertical Double‐Diffused Metal‐Oxide‐Semiconductor Field‐Effect Transistor with Enhanced Device Performance

A 4H-SiC Trench MOS Capacitor Structure for Sidewall Oxide Characteristics Measurement

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Interface Chemistry and Defect State Optimization of the ErSmO/InP Heterojunction Modified by ALD-Driven Al₂O₃ Interlayers

Interface Chemistry and Defect State Optimization of the ErSmO/InP Heterojunction Modified by ALD-Driven Al₂O₃ Interlayers