Study of Warpage Evolution and Control for Six-Side Molded WLCSP in Different Packaging Processes

Qin, Fei; Zhao, Shuai; Dai, Yanwei; Yang, Mengke; Xiang, Min

doi:10.1109/tcpmt.2020.2975571

Cited by 18 publications

(3 citation statements)

References 26 publications

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“…Several techniques are used to measure the distance between the neighbors. Two simple techniques are used in this study: the Euclidean distance function d(x, y), provided in Equation ( 12), and the Manhattan distance function d(x, y), provided in Equation (13).…”

Section: Knn Modelmentioning

confidence: 99%

“…With the increasing complexity of packaging structures, manufacturing reliability test vehicles, and conducting ATCT experiments have become time-consuming and very expensive processes, the design-on-experiment (DoE) methodology for packaging design is becoming infeasible. As a result of the wide adoption of finite element analysis [ 9 , 10 , 11 , 12 , 13 , 14 , 15 ], accelerated thermal cycling tests are reduced significantly in the semiconductor industry, and package development time and cost are reduced as well. In a 3D WLP model, Liu [ 16 ] applied the Coffin–Manson life prediction empirical model to predict the reliability life of a solder joint within an accurate range.…”

Section: Introductionmentioning

confidence: 99%

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An Overview of AI-Assisted Design-on-Simulation Technology for Reliability Life Prediction of Advanced Packaging

et al. 2021

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Several design parameters affect the reliability of wafer-level type advanced packaging, such as upper and lower pad sizes, solder volume, buffer layer thickness, and chip thickness, etc. Conventionally, the accelerated thermal cycling test (ATCT) is used to evaluate the reliability life of electronic packaging; however, optimizing the design parameters through ATCT is time-consuming and expensive, reducing the number of experiments becomes a critical issue. In recent years, many researchers have adopted the finite-element-based design-on-simulation (DoS) technology for the reliability assessment of electronic packaging. DoS technology can effectively shorten the design cycle, reduce costs, and effectively optimize the packaging structure. However, the simulation analysis results are highly dependent on the individual researcher and are usually inconsistent between them. Artificial intelligence (AI) can help researchers avoid the shortcomings of the human factor. This study demonstrates AI-assisted DoS technology by combining artificial intelligence and simulation technologies to predict wafer level package (WLP) reliability. In order to ensure reliability prediction accuracy, the simulation procedure was validated by several experiments prior to creating a large AI training database. This research studies several machine learning models, including artificial neural network (ANN), recurrent neural network (RNN), support vector regression (SVR), kernel ridge regression (KRR), K-nearest neighbor (KNN), and random forest (RF). These models are evaluated in this study based on prediction accuracy and CPU time consumption.

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Section: Knn Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An Overview of AI-Assisted Design-on-Simulation Technology for Reliability Life Prediction of Advanced Packaging

et al. 2021

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“…This WLP technique is a real chip-scale packaging method that enables packages to maintain the same size as a die. A new efficient WLP technique created a gas-filled cavity structure for SAW filter packages, using non-photosensitive film lamination technology, with high strength and a high elastic modulus [ 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 19 ].…”

Section: Process Flow Of the Saw Device’s Wlp And The Typical Failure...mentioning

confidence: 99%

Development of a Reliable High-Performance WLP for a SAW Device

Chen

2022

Sensors

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In this paper, we present wafer-level packaging technology for surface acoustic wave (SAW) filters with higher long-term reliability and better electrical performance. This article focuses on the package structure, fabrication processes, and reliability for the SAW filter wafer-level package (WLP). The key processes, including cavity wall (CW) dam formation through non-photosensitive film vias development using a laser drilling process, a redistribution layer (RDL), and ball-grid array formation are developed. In addition, a numerical study based on the finite element model has been conducted to analyze the stress distribution of Cu RDL traces. In addition, the CW dam and the roof layer are covered with polymer, which solves the delamination problem between the CW dam and the substrate. Meanwhile, after practical verification, the SAW filter WLP was resistant to encapsulating pressure using a high elastic modulus capping material, which solved the collapse problem. Additionally, a comparison of the RF filter package’s electrical performance following the preconditional level 3 and unbiased highly accelerated stress test revealed no differences in insertion attenuation across the passband (<0.2 dB, standard value: 1 dB). The final packages passed the reliability tests in the field of consumer electronics.

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Fan-In Wafer/Panel-Level Chip-Scale Packages

Lau

2021

Semiconductor Advanced Packaging

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Study of Warpage Evolution and Control for Six-Side Molded WLCSP in Different Packaging Processes

Cited by 18 publications

References 26 publications

An Overview of AI-Assisted Design-on-Simulation Technology for Reliability Life Prediction of Advanced Packaging

An Overview of AI-Assisted Design-on-Simulation Technology for Reliability Life Prediction of Advanced Packaging

Development of a Reliable High-Performance WLP for a SAW Device

Fan-In Wafer/Panel-Level Chip-Scale Packages

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