Traditional designs of high bandwidth frequency synthesizers employ the use of a phase locked-loop. A direct digital synthesizer (DDS) provides many significant advantages over the PLL approaches. The thesis emphasizing discusses the designing of DDS basing on FPGA. DDS is made up of the phrase accumulator and sine ROM looking-up table, which is realized by functional EAB chip. And through setting different initial accumulator value and initial phrase value, the difference of phrase between the two sine signals can be changed. As a result, two serials of sine signals with changeable digital frequency, phrase and magnitude are produced. The simulate results show that logic in FPGA is consistent with the requirements.