Study on Retest Reduction by Minimizing Probe Card Contact Resistance at Wafer Test

Li, Hua; Zheng, Deguang

doi:10.1109/cstic52283.2021.9461487

Cited by 5 publications

(3 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In reality during the testing process, an appropriate TGB can be used to determine the quality and quantity of products delivered to consumers. In the semiconductor IC testing industry, retesting methods have been applied during production to improve post-test yields [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19]. For example, we refer to the paper of Kirmse et al [17].…”

Section: Test Overall Timing Accuracy and Tgb Impact On The Test Resultsmentioning

confidence: 99%

“…In the semiconductor IC testing industry, retesting methods have been applied during production to improve post-test yields [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19]. For example, we refer to the paper of Kirmse et al [17].…”

Section: A New Methods For Test Yield Improvement: Multiplex Testingmentioning

confidence: 99%

“…Therefore, suppliers must propose good methods to solve this problem. Currently, in the semiconductor testing industry, retesting is being applied in the production process to improve test results [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19]. In the actual test in the test factory, the retest strategy greatly improves the test yield.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield

Yeh¹,

Chen²,

Chang³

et al. 2022

Electronics

View full text Add to dashboard Cite

In this work, we use statistical concepts to evaluate the joint probability distribution of manufacturing and test parameters and estimate the future trend of wafer test yield. Owing to the difference between the development speeds of testing technology and manufacturing technology, the testing capability of wafers is far behind the manufacturing capability of the semiconductor. Therefore, with the advancement in technology, the test yield loss caused by the tester inaccuracy has become an important problem. In this article, we propose an enhanced integrated circuit (IC) test scheme (ITS) that uses multiplex testing to improve test quality and test pass rate by retesting, and we rely on the cost evaluation mechanism to obtain the best test and the best profit. Furthermore, the International Roadmap for Devices and Systems (IRDS) 2017 data are used to estimate future test yield trends, and the results prove that the enhanced test scheme (ETS) can effectively estimate the best retest time to obtain the best test yield and the best profit.

show abstract