Study on signal conditioning technology in 2GHz broadband digital oscilloscope

Qiu, Duyu; Tian, Shulin; Zeng, Hao; Pan, Huiqing

doi:10.1109/icemi.2013.6743069

Cited by 5 publications

(6 citation statements)

References 1 publication

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“…Tai klasikinė realiojo laiko oscilografo stiprintuvo struktūra, naudojama daugelyje 0,1-5 GHz oscilografų. Ši struktūra išsamiai aprašoma daugelyje publikuotų mokslinių darbų, pvz., Jiang ir Liu (2017), Duyu et al (2011Duyu et al ( , 2013, Li et al (2011). Iš 1 paveiksle pateiktos struktūros matyti, kad matuojamas signalas patenka į ateniuatorių.…”

Section: Oscilografo įėJimo Stiprintuvo Paskirtis Ir Struktūraunclassified

“…Valdomas stiprintuvas skirtas įėjimo signalui stiprinti iki ASK įėjimo dinamikos. Šios grandies stiprinimo koefi cientas tiesiogiai nulemia oscilografo vertikaliosios skalės jautrumo diapazoną ir dažniausiai pasižymi 0−40 dB stiprinimo koefi ciento diapazonu (Duyu et al, 2013). Toks stiprinimo koefi cientas šiuo metu gali būti pasiektas tik naudojant kelių stiprinimo kaskadų nuoseklųjį jungimą.…”

Section: Oscilografo įėJimo Stiprintuvo Paskirtis Ir Struktūraunclassified

“…Ateniuatoriaus, įėjimo apsaugos ir buferinė grandinės kartu vadinamos impedanso pakeitimo grandine (Duyu et al, 2013). Žinoma, kad oscilografo impedanso pakeitimo grandinė turi užtikrinti vienodą perdavimo koefi cientą esant tiek DC (angl.…”

Section: Oscilografo įėJimo Stiprintuvo Paskirtis Ir Struktūraunclassified

“…Pakankamos pralaidumo juostos mikroschemos arba neturi DC stiprinimo, arba turi neizoliuotą stiprinimo valdymą, kuris neleidžia įgyvendinti korektiško DC poslinkio. Vienas iš galimų šios problemos sprendimo būdų -matuojamą signalą suskaidyti į žemojo ir aukštojo dažnio komponentus (Duyu et al, 2013). Atskiros signalo dalys stiprinamos skirtingose grandinės dalyse, o vėliau sujungiamos naudojant pasirinktą sumatoriaus konfi gūraciją.…”

Section: Oscilografo įėJimo Stiprintuvo Paskirtis Ir Struktūraunclassified

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Development and Investigation of Input Amplifier for the Osciloscope

Borel

2020

Science - Future of Lithuania

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Digital oscilloscope’s structure has analog signal acquisition circuit, which transforms signal’s amplitude to fit ADC dynamic range. This circuit is commonly called oscilloscope’s vertical or front-end amplifier. Difficulty in designing front-end amplifiers in GHz range largely affects higher frequency range oscilloscope’s price. This work is focused on designing a front-end amplifier using discrete and openly sold components. We propose a design for attenuator, buffer, variable gain circuits. Amplifier’s prototype is designed. Main characteristics of the amplifier were measured. Measured bandwidth is 3 GHz. Amplifier’s gain and attenuation can support vertical scale sensitivity range from 10 mV/div to 1 V/div. Step response distortion is under 10 %. SMD and PTH relay model attenuators were evaluated. In this paper we review oscilloscope’s front-end purpose and structure. We review amplifiers design and provide the results of experimental measurements.

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Section: Oscilografo įėJimo Stiprintuvo Paskirtis Ir Struktūraunclassified

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Development and Investigation of Input Amplifier for the Osciloscope

Borel

2020

Science - Future of Lithuania

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“…Various contributions deal with the very complex software structure of the instruments that are equipped with complete operating systems and a series of dedicated software modules, [4]- [6], while other research activities are oriented to the whole circuital structure of the DSO, [7]- [23]. Many papers study and improve the front-end of the DSO as this is the portion that determines the sampling rate and the bandwidth, [7]- [11]. Other contributions propose various sampling methods and real-time or off-line processing that, exploiting the peculiarities of the signals and the front-end, allow an extension of the bandwidth or an improvement of the resolution, [12]- [19].…”

Section: Introductionmentioning

confidence: 99%

Real-Time Downsampling in Digital Storage Oscilloscopes With Multichannel Architectures

Napoli

Zacharelos

D’Arco

et al. 2021

IEEE Trans. Circuits Syst. I

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Digital Storage Oscilloscopes (DSOs) conjugate high performance with large number of features and flexibility. The basic structure, based on fast Analog to Digital Converter (ADC) and memory, is augmented with several components for channel matching and bandwidth improvement, and processors that provide visualization, frequency processing, jitter and stability measurement, etc. Unfortunately, fine resolution in sample rate selection is not available, such that for several applications the user must run complex measurement procedures that require data download and offline processing. The paper proposes a dedicated digital circuit that offers fine control of the time-base by real time downsampling the input stream at an almost arbitrary sampling rate. The proposed circuit implements a series of operations involving real-time data filtering, defragmentation and packing, which are not considered by alternative approaches, like those based on polyphase filters, that offer very limited choices for the sampling rate. The circuit is designed to work in conjunction with the highest performance DSOs that use a multichannel architecture. Design rules for circuit design are provided together with implementation results in 14nm FinFET technology. When designed for an architecture with 64 channels with 8bit input samples the circuit works in real time with a sampling rate of 220 GSps running at 3.42 GHz, with a silicon footprint of 0.17 mm 2 and a power dissipation of 0.85W.

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