Study on the Effects of Wafer Thinning and Dicing on Chip Strength

Abstract

Die cracking is an annoying problem in the packaging industry. In this paper, we identified the weak regions, in terms of mechanical strength, in chips in a semiconductor wafer using the three-point bending test. The weak regions were observed in two sectors approximately 45 wide, axisymmetric to the wafer center. The strength of the chips within these weak regions was about 30%-35% lower than the average chip strength of the whole wafer. The existence of these weak regions was related to spiral grinding marks, which, in turn, were formed by backside mechanical grinding. The probability distributions of the chip strength and the chip fragmentary pattern confirmed this relationship. When wafers were mechanically ground until they were 50-m thick, chip warpage was found to be oriented to the direction of the grinding marks. Meanwhile, by slowing the mechanical grinding speed by 50%, we were able to increase the average chip strength by 56%. Either plasma etching or polishing after mechanical grinding eliminated the weak regions, and the optimal amount of mechanical grinding and the polishing depths were observed, beyond which the chip strength would not increase. On the other hand, a preprocess for blunting a new saw blade for chip dicing was found to be essential as the chip strength increased five-fold, whereas increasing the dicing speed or using dual saw instead of a single saw had only small effects on the chip strength degradation.

Thinning and readout during bending of a custom silicon IC

“…Thinning by mechanical grinding might be the most cost-effective method [8], but plasma etching will create smaller irregularities in the chips surfaces than what could be achieved by grinding or polishing. Irregularities induced in the chips surface would weaken the silicon strength [9], while reducing the minimum curving radius causing fracture. For this study, the ALPIDE thickness was selected to 45µm, a value close to the minimum, while leaving a safety margin, to reduce the risk of fractures during handling.…”

Out-of-plane neural microelectrode arrays fabrication using conventional blade dicing

“…Depending on the material, it can exhibit different behavior when diced. Typically, semiconductors like silicon, ceramics, and glasses present brittle mode cutting, which frequently induce microcracks within the material and chipping occurs at the edges [21,22]. The minimization of these effects has been a priority fabrication issue.…”

Dicing of composite substrate for thin film AlGaInP power LEDs by wet etching

“…Nevertheless, a CuW metal substrate is expensive, it is difficult to achieve a thickness below 150 μm, and it is hard to dice by dicing saw and laser. Concerning the Si permanent substrate, it is necessary to perform more processes, such as lapping Si substrate to a 150-μm thickness, depositing the Al metal, and performing thermal annealing (to obtain the Ohmic contact property between the Al metal and Si) 8 , 9 . If the thickness of Si substrate is too thin (< 150 μm), the cracking phenomenon of the LED epilayer could often occur during the processing.…”

“…Damage to the LED chips during laser and saw dicing is a serious issue. This technology faces a number of challenges to meet demands for next-generation device manufacturing processes, including chipping and cracking of the dice, limitations in street width, limitations in die shape, mechanical stress of the dies, and limitations in processed materials 15 , 16 . To overcome these problems, wet chemical etching dicing, which is a novel substrate level dicing method for low cost and high-performance LEDs, was proposed.…”