2016
DOI: 10.1038/srep24734
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Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor

Abstract: Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-kT/q subthreshold slope (SS) is significantly important to the development of next generation active-matrix organic-light emitting diode displays. This is the first time a sub-kT/q SS (31.44 mV/dec) incorporated with a LTPS-TFT with polycrystalline-Pb(Zr,Ti)O3 (PZT)/ZrTiO4 (ZTO) gate dielectrics has been demonstrated. The sub-kT/q SS was observed in the weak inversion region at −0.5 V showing ultra-low operating volt… Show more

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Cited by 28 publications
(18 citation statements)
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“…Experimental attempts to demonstrate steep slope operation (that is, S < 60 mV per decade) have focused on two approaches: direct integration of the ferroelectric into the gate stack and external connection of a ferro electric capacitor to a FET [71][72][73][74][75][76] . In the context of NCFETs, organic poly(vinylidenefluoridetrifluoroethylene) gate ferroelectrics [77][78][79] and perovskite PbZr 1−x Ti x O 3 (PZT) gates 80,81 were explored for direct integration, whereas Aurivilliusphase SrBi 2 Ta 2 O 9 (SBT), one of the most popu lar choices for FeFETs and ferroelectric randomaccess memories, appears to have been overlooked. Although perovskite oxides can be directly grown on semiconduc tors 82 , the unfavourable band alignment 83 and interface states at the metal-ferroelectric (M-F) interface usually require the insertion of a dielectric buffer layer, result ing in an MFIS or MFMIS stack (where I and S are the insulating buffer and semiconductor, respectively).…”
Section: Device Implementation Work On Ferroelectric Fetsmentioning
confidence: 99%
“…Experimental attempts to demonstrate steep slope operation (that is, S < 60 mV per decade) have focused on two approaches: direct integration of the ferroelectric into the gate stack and external connection of a ferro electric capacitor to a FET [71][72][73][74][75][76] . In the context of NCFETs, organic poly(vinylidenefluoridetrifluoroethylene) gate ferroelectrics [77][78][79] and perovskite PbZr 1−x Ti x O 3 (PZT) gates 80,81 were explored for direct integration, whereas Aurivilliusphase SrBi 2 Ta 2 O 9 (SBT), one of the most popu lar choices for FeFETs and ferroelectric randomaccess memories, appears to have been overlooked. Although perovskite oxides can be directly grown on semiconduc tors 82 , the unfavourable band alignment 83 and interface states at the metal-ferroelectric (M-F) interface usually require the insertion of a dielectric buffer layer, result ing in an MFIS or MFMIS stack (where I and S are the insulating buffer and semiconductor, respectively).…”
Section: Device Implementation Work On Ferroelectric Fetsmentioning
confidence: 99%
“…Specifically, the series structure offers a step-up voltage transformer that brings an abrupt increase in the differential charge of the internal node ( V int ). Accordingly, an NC booster provides an internal voltage amplification ( ∂V int / ∂V gate ), which results in a body factor reduction and a value of SS below the thermal limit of conventional MOSFETs. , …”
Section: Voltage Pinning Effect In Ferroelectric Gate Stacksmentioning
confidence: 99%
“…9 Especially recently, the NC effect has been increasingly investigated as it is considered one of the most promising mechanisms for overcoming the limitations of transistors. [10][11][12][13][14] In 2008, S. Salahuddin and S. Datta theorized a low-power nanoscale device that utilizes the ferroelectric NC effect to amplify gate voltage. 7 Continuing experiments on NCFETs over the past 10 years have improved this device.…”
Section: Introductionmentioning
confidence: 99%