Sub-surface Damage of Ultra-Thin Monocrystalline Silicon Wafer Induced by Dry Polishing

Zhang, Xundi; Yang, Chenlin; Zhang, Yumei; Hu, Anmin; Li, Ming; Gao, Liming; Ling, Huiqin; Hang, Tao

doi:10.1007/s13391-020-00226-z

Cited by 11 publications

(5 citation statements)

References 43 publications

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“…Freshly etched Si(100) shows an average root-mean-square surface roughness R q = 3.534 ± 0.535 Å, similar to other reports on HF-etched Si(100) surfaces. − BOE-etched Si(100) is usually atomically rough due to the evolution of Si(111) facets and Si(100) terraces during etching . Meso-scale height variation is observed (maximum height <1 nm), typical of dry-polished Si wafers − (Supporting Information, Figure S4, right). Upon treatment with Pt(dvs), R q increases to 5.252 ± 1.803 Å.…”

Section: Resultssupporting

confidence: 89%

Pt-Coated Silicon Nanoparticles: An Investigation into the Hydrosilylation on Hydrogen-Terminated Silicon Surfaces Using Pt(dvs)

et al. 2023

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The interaction of hydrogen-terminated silicon nanoparticles (H-SiNPs) with Karstedt's catalyst at various temperatures was investigated. The results indicate that at room temperature, the oxidative addition of Pt(0) onto H-SiNPs is irreversible, and the catalyst is not eliminated from the surface of H-SiNPs, enabling a facile synthesis of Pt-loaded SiNPs that can undergo ligand exchange. The nature of the Pt-on-Si ensemble is characterized by Fourier transform infrared spectroscopy, X-ray photoelectron spectroscopy, transmission electron microscopy, and energy-dispersive X-ray spectroscopy. Reaction conditions that enable effective hydrosilylation are discussed. It is found that higher temperatures favor reductive elimination of the catalyst and hydrosilylation of 1-octene onto the surface of the H-SiNPs.

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Section: Resultssupporting

confidence: 89%

Pt-Coated Silicon Nanoparticles: An Investigation into the Hydrosilylation on Hydrogen-Terminated Silicon Surfaces Using Pt(dvs)

et al. 2023

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“…In addition, damaged region may act as a gettering site, which is well-known for Si substrate. 45,46 Hence, the concentration of impurities may have chance to increase at the subsurface damage layers during the annealing.…”

Section: Discussionmentioning

confidence: 99%

Chemical Mechanical Polishing of MgO Substrate and Its Effect on Fabrication of Atomic Step-Terrace Structures on MgO Surface by Subsequent High-Temperature Annealing

Ojima¹,

Oshima²,

Ihara³

et al. 2022

ECS J. Solid State Sci. Technol.

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Single-crystalline MgO is used as a substrate for the deposition of various functional thin films. The present study focused on the development of a complete sequence of fabricating atomic step-terrace structures on the MgO substrate via a method that includes grinding, precise mechanical polishing, chemical mechanical polishing (CMP), and high-temperature annealing. The effect of a damage-free surface pretreatment on the subsequent high-temperature annealing was investigated. An atomically smooth and damage-free MgO substrate surface with an average surface roughness of 0.05 nm was obtaining via a CMP process using a colloidal silica slurry. Atomic step-terrace structures were formed on the substrate after the high-temperature annealing process at 1000℃ for 20 h under atmospheric air. The obtained step height was 0.20 nm, which corresponds to one-half the unit cell of an MgO crystal (0.21 nm). By contrast, when a mechanically damaged MgO substrate was subjected to the annealing process, Ca segregation was observed on the annealed surface, without the formation of an atomic step-terrace structure. CMP was found to be necessary prior to high-temperature annealing to attain a atomic step-terrace structures and to avoid the out-diffusion of impurities in the MgO bulk crystals.

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“…There were n linear equations corresponding to the n points and there were m variables to be determined in the system of linear equations. The system of linear equations could be transformed into a matrix equation [13], which is shown in Equation (3).…”

Section: Principle Of Residual Stress Obtainmentmentioning

confidence: 99%

“…With the lithographic line width reaching the physical limit, integrated circuit chips are shifting from transistor scaling to three-dimension integration [1,2]. Silicon wafer thinning is needed to satisfy the demand for three-dimension integrated circuits packaging since the primary wafer thickness is relatively large to retain enough stiffness [3,4]. Grinding is the commonly used technique to remove redundant material for its high efficiency [5].…”

Section: Introductionmentioning

confidence: 99%

Obtainment of Residual Stress Distribution from Surface Deformation under Continuity Constraints for Thinned Silicon Wafers

et al. 2021

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Precision machining (e.g., fine grinding, polishing) induced residual stress is very small and often not constant across the wafer and it is difficult to be directly obtained by stress testing equipment or Stoney equation. The residual stress could be obtained theoretically based on the principle of superposition in which the entire wafer deformation is taken as the sum of all deformations induced by the residual stresses of different positions on the wafer surface. However, the solved residual stress is affected greatly by deformation measurement errors and fluctuates greatly across the wafer surface. To solve the problem, a regularization method with continuity constraints was proposed in this study. The mechanisms for the discontinuity of the residual stress distribution and the sensitivity of calculation results to the measurement errors were studied. The influences of the number of subareas of the silicon wafer were investigated and the continuity constraint term was constructed based on the positional relationship of different subareas. Stable and continuous residual stress distribution was successfully obtained after using the proposed regularization method. The method may also be applied to estimate the residual stress from surface deformation for thin substrate plates of other materials.

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Sub-surface Damage of Ultra-Thin Monocrystalline Silicon Wafer Induced by Dry Polishing

Cited by 11 publications

References 43 publications

Pt-Coated Silicon Nanoparticles: An Investigation into the Hydrosilylation on Hydrogen-Terminated Silicon Surfaces Using Pt(dvs)

Pt-Coated Silicon Nanoparticles: An Investigation into the Hydrosilylation on Hydrogen-Terminated Silicon Surfaces Using Pt(dvs)

Chemical Mechanical Polishing of MgO Substrate and Its Effect on Fabrication of Atomic Step-Terrace Structures on MgO Surface by Subsequent High-Temperature Annealing

Obtainment of Residual Stress Distribution from Surface Deformation under Continuity Constraints for Thinned Silicon Wafers

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