Sub-Threshold Design: The Challenges of Minimizing Circuit Energy

Calhoun,; Wang, Hong; Verma, Subhash; Chandrakasan,

doi:10.1109/lpe.2006.4271869

Cited by 18 publications

(13 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Many burst-mode applications require high performance for brief time periods between extended sections of low performance operation [6]. Digital circuits supporting such burst-mode applications should work on both near-threshold regions and super-threshold regions for brief time periods.…”

Section: Introductionmentioning

confidence: 99%

Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control

Wang

Lin

et al. 2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

FinFET has been proposed as an alternative for bulk CMOS in the ultra-low power designs due to its more effective channel control, reduced random dopant fluctuation, higher ON/OFF current ratio, lower energy consumption, etc. The characteristics of FinFETs operating in the sub/near-threshold region are very different from those in the strong-inversion region. This paper introduces an analytical transregional FinFET model with high accuracy in both subthrehold and near-threshold regions. The unique feature of independent gate controls for FinFET devices is exploited for achieving a tradeoff between energy consumption and delay, and balancing the rise and fall times of FinFET gates. This paper proposes an effective design framework of FinFET standard cells based on the adaptive independent gate control method such that they can operate properly at all of subthreshold, near-threshold and super-threshold regions. The optimal voltage for independent gate control is derived so as to achieve equal rise and fall times or minimal energy-delay product at any supply voltage level.

show abstract

Section: Introductionmentioning

confidence: 99%

Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control

Wang

Lin

et al. 2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

show abstract

“…Many burst-mode applications require high performance for brief time periods between extended sections of low performance operation [6]. Digital circuits supporting such burst-mode applications should work in both the near-threshold region and super-threshold region (for brief time periods.)…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, traditional dynamic voltage scaling (DVS) method should be extended to include near-threshold operation, but the overhead of providing the necessary voltages can be large. Adjustable DC-DC converters tend to have limited efficiency over broad output voltage ranges, and they take hundreds of micro-seconds to switch between different supply levels especially in the nearthreshold regime [6]. An alternative implementation approach called local voltage dithering (LVD) uses header power switches to connect circuit blocks to one of the several power supply rails, thereby allowing for faster switching [7] [8].…”

Section: Introductionmentioning

confidence: 99%

Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power rails

Wang

Lin

Pedram

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

Many burst-mode applications require high performance for brief time periods between extended sections of low performance operation. Digital circuits supporting such burst-mode applications should work in both the near-threshold regime and the super-threshold regime for brief time periods. This work proposes the structure support of fine-grained ultra dynamic voltage scaling (UDVS) from the traditional strong-inversion region to the near-threshold region, with limitations on the number of power rails. The number, type, and size of the power switches are jointly optimized to minimize the overall energy consumption of the UDVS circuit block, meanwhile satisfying the target delay or frequency requirement at each DVS level. The proposed optimization framework properly accounts for the dynamic energy consumption as well as the leakage energy consumption through all the power switches during both the operation time and stand-by time of the circuit block. Experimental results on 22nm Predictive Technology Model demonstrate the effectiveness of the proposed optimization framework.

show abstract

“…As integrated biosensor systems often require very low power consumption to extend battery life and to maintain low cost, power requirement for storage arrays in the integrated biosensor systems is a key measure of system performance and should be kept as low as possible. One of the most effective methods to reduce power consumption is to reduce supply voltage to near transistor's threshold voltage, V t , or even below V t [19], [20].…”

Section: Introductionmentioning

confidence: 99%

“…Operating biosensor circuits near or below V t has been proven to be effective for digital logic gates [19], [20], [21]. However, the impact of operating at a very low supply voltage for storage circuits is still an open question due to the significantly deteriorating reliability under a very low supply voltage and more investigations are needed.…”

Section: Introductionmentioning

confidence: 99%

On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications

Chen

Hoppal

2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

View full text Add to dashboard Cite

Storage arrays are widely used in integrated biosensor systems to store detected signals before and after they are processed. As integrated biosensor systems often require very low power consumption to extend battery life and to maintain low cost, power consumption for storage arrays in integrated biosensor systems should be kept low, whereas the speed requirement is usually not high such that state-of-the-art IC technology is not usually needed. This paper presents the results of our investigation of designing low power memory structures in sub 1-V operation with high reliability for biosensor systems. Rather than using the state-of-the-art 45nm/32nm technology, 0.18 μm CMOS technology is used for the design to keep the overall cost down while achieving read and write performance of 200MHz cycle rate. The results show that the use of body back bias in systems with low supply voltage can improve memory's static noise margin (SNM) and memory write performance by as much as 25%.

show abstract

Sub-Threshold Design: The Challenges of Minimizing Circuit Energy

Cited by 18 publications

References 0 publications

Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control

Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control

Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power rails

On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications

Contact Info

Product

Resources

About