Submicron InP/InGaAs Composite-Channel Metal–Oxide–Semiconductor Field-Effect Transistor with Selectively Regrown n⁺-Source

Abstract

We have demonstrated an InP/InGaAs composite-channel metal–oxide–semiconductor field-effect transistor with a selectively regrown n+-InGaAs source/drain formed by metal organic vapor-phase epitaxy. A 150-nm-long channel was fabricated using a dummy gate and by laterally buried regrowth in the channel undercut. The gate stack was formed after regrowth by replacing the dummy gate. The carrier density of the regrown layer was 4.9×1019 cm-3. The maximum drain current at a drain voltage Vd = 1 V and a gate voltage Vg = 3 V was 0.93 mA/µm and the maximum transconductance was 0.53 mS/µm at Vd = 0.65 V.

InGaAs MOSFET source structures toward high speed/low power applications

“…Thus, InGaAs regrown sources were reported [8][9][10][11] and selective regrowth was required. On the other hand, when we used an n-InP source, a structure similar to the InGaAs-raised structure was fabricated by using single epitaxial growth and InP selective etching.…”

Poisson-Schroedinger-Continuity two-dimensional analysis of both short (ballistic) and long (drift-diffusion) III–V FETs

“…Such expectations are based on the superior mobilities of these materials as summarized in detail in [1]. The research activity in these type of devices has been intense [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. Originally the focus was on inversion type devices [2][3] but very soon these type of III-V FETs were abandoned in favor of devices with intrinsic channels filled with electrons from a supply layer [4][5][6][7][8][9][10][11][12].…”

“…The research activity in these type of devices has been intense [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. Originally the focus was on inversion type devices [2][3] but very soon these type of III-V FETs were abandoned in favor of devices with intrinsic channels filled with electrons from a supply layer [4][5][6][7][8][9][10][11][12]. Furthermore long-gate FETs [4] were quickly substituted with nanometric gate FETs [5][6][7][8][9][10][11][12][13][14][15][16][17] and indeed, at the moment, 30-60nm gate length QW FETs with InGaAs channels exist having superior performance such as a subthreshold slope of 96mV/dec and a peak transconductance of 2.4mS/μm [9][10].…”

Au‐free Si MOS compatible Ni/Ge/Al ohmic contacts to n+‐InGaAs

“…For the practical integration of III–V MOSFETs on a Si CMOS platform, challenges include heteroepitaxy of III–V on Si substrates , high‐ k gate dielectric/metal gate stacks , and contact resistance of the source/drain electrodes . Of these challenges, source/drain contact resistance, which comprises most of the series resistance, plays an important role in the high transconductance of III–V MOSFETs.…”