Submicron T-shaped gate HEMT fabrication using deep-UV lithography

Chang, Edward Yi; Lin, Kuan Chou; Liu, E.H.; Chang, Chun Yen; Chen, T.H.; Chen, J.

doi:10.1109/55.296215

Cited by 20 publications

(4 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To break through the material limits of Silicon and to realize the drastic performance improvement needed to meet the severe requirements in the future, wide bandgap semiconductors such as SiC and GaN have attracted much attention because of their superior physical prosperities. AlGaN/GaN high electron mobility transistor (HEMT) were projected to have lower on-resistance and higher switching speed than SiC devices due to the high electron mobility and density of the two-dimensional electron gas(2DEG) formed in the AlGaN/GaN triangular potential quantum well [1][2][3] .…”

Section: Introductionmentioning

confidence: 99%

2DEG Transport Properties in AlGaN/GaN Double Heterostructure HEMT with High In Composition InGaN Channel

Peng¹,

Xiang²,

Li³

et al. 2013

AMR

View full text Add to dashboard Cite

AlGaN/InGaN/GaN double heterostructure high electron mobility transistor (HEMT) with In composition from 0.08 to 0.26 were grown by MOCVD. 2DEG density and mobility of different channel In composition were investigated. When In composition below 0.19, 2DEG density increased nearly linearly with In composition, and the mobility decreased a bit. While In composition over 0.19, phase separation became more serious, 2DEG density nearly not changed, and the mobility dropped sharply. A high 2DEG mobility of 1163 cm2/V·s with low sheet resistance of 342Ω/ was obtained with In composition 0.19.

show abstract

Section: Introductionmentioning

confidence: 99%

2DEG Transport Properties in AlGaN/GaN Double Heterostructure HEMT with High In Composition InGaN Channel

Peng¹,

Xiang²,

Li³

et al. 2013

AMR

View full text Add to dashboard Cite

show abstract

“…To obtain high gate control, the T‐shaped DG structure is utilized and gate length (L g ) of the device is fixed at 30 nm. By using this DG architecture, the SCEs in the device can be minimized . The gate‐source (L sg + L rs ) spacing is kept at 350 nm and the recess length of the gate at source side (L rs ) is kept constant at 30 nm and drain‐side recess length of the gate (L rd ) is varied from 40 to 60 nm to find the optimized value of f max by increasing the g ds .…”

Section: Device Architecturementioning

confidence: 99%

Sheet‐carrier density and I‐V analysis of In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As dual channel double gate HEMT for THz applications

Poornachandran¹,

Mohankumar²,

Kumar

et al. 2019

Int J Numerical Modelling

View full text Add to dashboard Cite

This paper gives a comprehensive detail about an emerging InAs high electron mobility transistor (HEMT) technology with proper material combination making it suitable for low-power and high-frequency applications. Over the decade, various material combinations were adopted to improve the sheetcarrier density and frequency performances. In this work, we report the performance and optimization of 30-nm gate length InAs-based dual channel double gate (DCDG) HEMT for terahertz application. The dual channel is formed in the device due to the combination of five layers (In 0.7 Ga 0.3 As/InAs/In 0.7 Ga 0.3 As/ InAs/In 0.7 Ga 0.3 As) and thus provides a significant improvement in drain current and transconductance. Moreover, the gate scaling with optimized gate to drainside recess length of gate (L rd ) leads to reduced parasitic (C gg ) and tremendously increases the RF performance metrics f max and f T . For this device, high drain current of 2.203 mA/μm with peak transconductance of 4.77 mS/μm is observed. Further optimization of L rd results in peak f T of 810 GHz and f max of 900 GHz at a drain source voltage V ds = 0.5 V. These parameters empower a feasibility of the device for submillimeter as well as terahertz applications.

show abstract

“…Tri-layer e-beam resist stacks have been used along with selective developers to create T-gate resist profiles using only a single exposure and develop step. 5,6 Another method used to fabricate T-gates involves the use of a negative resist as the bottom layer. The negative resist is patterned, and the cap portion is created using a second lithography step by an alignment and exposure of a second mask.…”

Section: Introductionmentioning

confidence: 99%

Bilayer and trilayer lift-off processing for i-line and DUV lithography

et al. 2002

View full text Add to dashboard Cite

Lift-off resist processing has been used for a variety of applications as a way of patterning metal layers using additive deposition methods. Many different processes have been used for this purpose, each involving either single or multiple layers of resist which are processed to form a reentrant profile. In this study, we examine two specific applications where lift-off processing is especially challenging. In the first case, a high resolution i-line lift-off process was needed for an application having severe surface topography caused by thick surrounding ohmic structures. Conventional bi-layer resist processing provided poor critical dimension control due to adjacent reflective surfaces and swing effects caused by resist thickness non-uniformity. A solution was found by incorporating a developable anti-reflective coating into the resist stack to reduce reflectance and resulting swing effects. The result was a lift-off process with high resolution used to image gate trenches over severe topology with critical dimension control maintained. The second application involved creating a T-gate profile using conventional optical lithography methods and modern positive DUV resists. Problems related to interlayer mixing and dissolution were overcome by introducing a photostabilization process to harden the stem layer and maintain its fidelity during the coating of subsequent resist layers. The result was an all optical, positive DUV tri-layer resist stack performed using two separate optical exposures, which produced a 200 nm T-shaped gate structure.

show abstract

Submicron T-shaped gate HEMT fabrication using deep-UV lithography

Cited by 20 publications

References 6 publications

2DEG Transport Properties in AlGaN/GaN Double Heterostructure HEMT with High In Composition InGaN Channel

2DEG Transport Properties in AlGaN/GaN Double Heterostructure HEMT with High In Composition InGaN Channel

Sheet‐carrier density and I‐V analysis of In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As dual channel double gate HEMT for THz applications

Bilayer and trilayer lift-off processing for i-line and DUV lithography

Contact Info

Product

Resources

About

Submicron T-shaped gate HEMT fabrication using deep-UV lithography

Cited by 20 publications

References 6 publications

2DEG Transport Properties in AlGaN/GaN Double Heterostructure HEMT with High In Composition InGaN Channel

2DEG Transport Properties in AlGaN/GaN Double Heterostructure HEMT with High In Composition InGaN Channel

Sheet‐carrier density and I‐V analysis of In0.7Ga0.3As/InAs/In0.7Ga0.3As/InAs/In0.7Ga0.3As dual channel double gate HEMT for THz applications

Bilayer and trilayer lift-off processing for i-line and DUV lithography

Contact Info

Product

Resources

About

Sheet‐carrier density and I‐V analysis of In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As dual channel double gate HEMT for THz applications