Substrate bias dependent leakage in LDD MOSFETs

Sweeney, J.; Herr, N.; Schani, P.; Mauntel, R.; Mendez, H.; Fejes, Peter; Parrillo, L.C.

doi:10.1109/iedm.1988.32798

Cited by 13 publications

(3 citation statements)

References 1 publication

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“…I. Mechanisms involved in the silicon consumption in CH 3 A loss of silicon in active source/drain regions of CMOS transistors can be observed during nitride spacer etch processes, employing CH 3 F/O 2 /He based chemistries in high density plasmas. I. Mechanisms involved in the silicon consumption in CH 3 A loss of silicon in active source/drain regions of CMOS transistors can be observed during nitride spacer etch processes, employing CH 3 F/O 2 /He based chemistries in high density plasmas.…”

mentioning

confidence: 99%

Patterning of silicon nitride for CMOS gate spacer technology. I. Mechanisms involved in the silicon consumption in CH3F/O2/He high density plasmas

Blanc¹,

Leverd²,

David³

et al. 2013

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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mentioning

confidence: 99%

Patterning of silicon nitride for CMOS gate spacer technology. I. Mechanisms involved in the silicon consumption in CH3F/O2/He high density plasmas

Blanc¹,

Leverd²,

David³

et al. 2013

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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“…I and 2). Gate edge line defects, originating in S/D regions and protruding under sidewall oxide, resemble defects reported to be responsible for electrical leakage and single bit failures (1)(2)(3)(4)(5). Gate edge defects are approximately 3 to 5• more numerous in B-implanted regions than in As-implanted regions.…”

Section: Resultsmentioning

confidence: 87%

Effect of Device Processing Conditions on Extended Dislocations and Defects in Ti‐Salicided Source/Drain Regions of Silicon Integrated Circuits

Guldi

1993

J. Electrochem. Soc.

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The propagation of incipient n+ and p+ source/drain (S/D) implant damage into extended dislocations at gate and field edges was studied for a variety of different processing conditions used to fabricate typical Ti‐salicided complimentory metal oxide semiconductor transistors. Gate edge dislocations were observed predominantly in n‐wells, while field edge defects occurred in both n and p‐wells. Both gate edge and field edge dislocations were found to be strongly affected by stresses from field oxide edges and overlying dielectric spacer layers. The use of a low‐stress polysilicon‐to‐metal dielectric is effective in reducing the density of extended dislocations in both n‐ and p‐wells. Moderation of field oxide edge stress, either by reducing the field oxide thickness or by tapering the field to active area transition region, is also effective in reducing dislocation density in the n‐well.

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“…The SiN x gate spacer formation is one of the key processes in the miniaturized metalinsulator-semiconductor field effect transistors (MISFETs), because the thickness of the gate spacer and the Si recess after the gate spacer formation etching have large impacts on the electrical properties of MISFETs (1)(2)(3). High selectivity of SiN x over Si is strongly required for the reduction of the series resistance in MISFETs such as the extremely thin silicon on insulator (ETSOI) device and FinFET.…”

Section: Introductionmentioning

confidence: 99%

High Selectivity in Dry Etching of Silicon Nitride over Si Using a Novel Hydrofluorocarbon Etch Gas in a Microwave Excited Plasma for FinFET

et al. 2014

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Increased etch selectivity of SiNx over Si is required for the gate spacer formation in miniaturized MISFETs, especially in the FinFET. In this work, the selectivity of SiNx over Si is evaluated using a novel hydrofluorocarbon etch gas with a microwave excited high-density plasma. By using this novel etchant gas, a higher selectivity of SiNx over Si was obtained compared to CH3F. The etch rate of Si was suppressed due to the deposition of a hydrocarbon film on Si surface without O2 gas. It was found that the selectivity of SiNx over Si near the SiNx sidewall decreased compared that far from the SiNx sidewall. By using flow rates of more than 12 sccm of the novel CxHyFz gas, the gate spacer was formed without Si recess even after the SiNx was overetched for an equivalent thickness of 40 nm.

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Substrate bias dependent leakage in LDD MOSFETs

Cited by 13 publications

References 1 publication

Patterning of silicon nitride for CMOS gate spacer technology. I. Mechanisms involved in the silicon consumption in CH3F/O2/He high density plasmas

Patterning of silicon nitride for CMOS gate spacer technology. I. Mechanisms involved in the silicon consumption in CH3F/O2/He high density plasmas

Effect of Device Processing Conditions on Extended Dislocations and Defects in Ti‐Salicided Source/Drain Regions of Silicon Integrated Circuits

High Selectivity in Dry Etching of Silicon Nitride over Si Using a Novel Hydrofluorocarbon Etch Gas in a Microwave Excited Plasma for FinFET

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