Substrate Network Modeling for Lateral p-GaN Gate HEMTs in a 200V GAN-IC Platform

Abstract

In a monolithically integrated GaN-IC, the parasitic inductance, capacitance and resistance between the driver and the half-bridge is greatly reduced. In a GaN-IC platform on SOI combined with oxide filled deep trench isolation, the backgating effect on the high-side power device is eliminated. Yet some issues related to the epitaxial stack and the substrate contact layer need to be addressed. In this paper, a substrate network concept is presented for 200V p-GaN gate HEMTs on SOI, and the impact of the epitaxial stack on device operation is investigated through modeling the epitaxial stack as a parallel R-C network. Double pulse tests were simulated and the impact on the substrate current was investigated. It is concluded that the substrate current peaks have a strong dependency on the epitaxial stack and the switching times, and that the peaks can be reduced by increasing the substrate layer resistivity.