Super-junction LDMOST on a silicon-on-sapphire substrate

Nassif-Khalil, S.G.; Salama, C.A.T.

doi:10.1109/ted.2003.813460

Cited by 98 publications

(42 citation statements)

References 9 publications

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“…However, it should be pointed out that, in order to reduce the process difficulty, the aspect ratio (pillar height/pillar width) of the proposed device is 5, which is only half aspect ratio of the SJ/R device. In fact, the on-resistance of SJ-LDMOS decreases with inverse proportion of aspect ratio [2]. Fig.…”

Section: Resultsmentioning

confidence: 91%

“…Lateral double-diffused MOSFETs (LDMOST) based on the super junction (SJ) concept were recently proposed to further improve the trade-off characteristics between the breakdown voltage (BV) and the on-resistance (R on ) which has always been a major issue in the design of power device [1][2][3][4][5][6]. The SJ concept is based on achieving charge compensation in the off-state, in a set of alternating and heavily doped n and p pillars comprising the drift region of the device.…”

Section: Introductionmentioning

confidence: 99%

“…To overcome this, it is possible to use silicon on sapphire (SOS) technology as a dielectric substrate. In that case, the interaction between the substrate and the SJ pillars is eliminated completely [2,3]. Unfortunately, the use of a sapphire substrate is expensive and not mainstream silicon technology.…”

Section: Introductionmentioning

confidence: 99%

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Realizing high voltage SJ-LDMOS with non-uniform N-buried layer

Chen

Zhang

2008

Solid-State Electronics

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Section: Resultsmentioning

confidence: 91%

Section: Introductionmentioning

confidence: 99%

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Realizing high voltage SJ-LDMOS with non-uniform N-buried layer

Chen

Zhang

2008

Solid-State Electronics

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“…To reduce the effect of substrate depletion on breakdown voltage, SJ-LDMOS on a silicon on sapphire substrate and a combination of superjunction and RESURF LDMOS are proposed [60,61]. Another approach is to design shallow pillars and place an "N-buffer layer" between the pillars and the substrate in Fig.…”

Section: The Superjunction Conceptmentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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This chapter focuses mainly on the drain-extended MOS transistor, DEMOS, for high voltage applications, and on the lateral double-diffused MOS transistor, LDMOS, for high power applications. In both cases, the drain is extended with a lightly-doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface-field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation, body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications. IntroductionThe MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium voltage range of about 0.8-6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS transistor (DEMOS), for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, LDMOS, for power applications. (The "D" in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same oxide opening, defining a precise channel length (Chap. 9). The "L" means that the current path is parallel to the silicon surface (lateral), as opposed to "V" in VDMOS where the current is nearly vertical to the silicon surface.) Schematic cross sections of both transistors (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics, automotive electronics, and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1][2][3][4][5].This chapter focuses mainly on transistors with voltage capabilities in the range of 20-700 V, where the bulk of the product applications lie.

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“…However, as the device size is reduced the energy handling capability is becoming very important issue to be addressed together with the tradeoff between on-resistance and breakdown voltage. Although there exists many structlllC S and concepts how to solve those requirements [2,3] the internal behavior of the device is still not completely unders tood and a strong effort is devoted to numerical modeling and simulation �,5l In this work we present the results of nun1crical simulation of the combined electro.…”

Section: Introductionmentioning

confidence: 99%

Analysis of the electrical and thermal properties of power DMOS devices during UIS supported by 2 - D process and device simulation

Donoval¹,

Vrbicky²

The Fifth International Conference on Advanced Semiconductor Devices and Microsystems, 2004. ASDAM 2004.

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Analysis oj the electrical and thermal properties oj power DMOSFET devices based on the 2-D mixed mode modeling and simulation is presented. The physical behavior oj the device structure during undamped inductive switching (UlS) is studied on the multicel! structure with good and bad cells. The "bad" cell is dejined by the higher series resistance attached to the ptype well: The higher voltage drop on the bad cell turns the parasitic bipolar transistor on and large current starts to flow via bad cell. The generated heat and corresponding temperature growth opens the next parasitic bipolar transistor in the adjacent cell. Due to further inaease of current more heat is generated (a positive feedback). We observed that an increase of series resistance, e. g. due to fluctuations of contact resista nce and specific resistance of frtype well could create such a weak spot in the device which jinalJy leads to the device failure.

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Super-junction LDMOST on a silicon-on-sapphire substrate

Cited by 98 publications

References 9 publications

Realizing high voltage SJ-LDMOS with non-uniform N-buried layer

Realizing high voltage SJ-LDMOS with non-uniform N-buried layer

High-Voltage and Power Transistors

Analysis of the electrical and thermal properties of power DMOS devices during UIS supported by 2 - D process and device simulation

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