Super Junction MOSFETs above 600V with Parallel Gate Structure Fabricated by Deep Trench Etching and Epitaxial Growth

Sugi, A.; Takei, Masahiro; Takahashi, Kensuke; Yajima, A.; Tomizawa, H.; Nakazawa, Hiroyuki

doi:10.1109/ispsd.2008.4538924

Cited by 11 publications

(6 citation statements)

References 5 publications

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“…1,2) Specifically, MOSFETs with a superjunction (SJ) structure (SJ-MOSFET) has been developed as a device to overcome the unipolar limit. 3,4) Although SJ-MOSFETs have already been commercialized in Si, [3][4][5][6] SiC SJ-MOSFET has never been commercialized and their characterization is required for commercialization.…”

Section: Introductionmentioning

confidence: 99%

Effects of ion implantation process on defect distribution in SiC SJ-MOSFET

Fukui¹,

Ishii²,

Tawara³

et al. 2023

Jpn. J. Appl. Phys.

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A superjunction (SJ) structure in power devices is compatible with low specific on-resistance and high breakdown voltage. To fabricate the SJ structure in SiC power devices, the repetition of ion implantation and epitaxial growth processes is a practical method. However, the impact of ion implantation on device performance has rarely been reported. In this study, we measured the carrier lifetime distributions in a SiC MOSFET with an SJ structure using a microscopic free carrier absorption method. Furthermore, we observed the distribution of defects via cathodoluminescence and deep levels via deep-level transient spectroscopy. We observed that Al ion implantation induced defects and reduced the carrier lifetime in the SJ structure. However, N ion implantation does not significantly induce defects. Additionally, Al ion implantation at room temperature exhibited more significant effects than implantation at 500°C. The results can aid in controlling the carrier lifetime in SiC SJ MOSFETs.

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Section: Introductionmentioning

confidence: 99%

Effects of ion implantation process on defect distribution in SiC SJ-MOSFET

Fukui¹,

Ishii²,

Tawara³

et al. 2023

Jpn. J. Appl. Phys.

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“…However, the narrow mesa would add to the difficulty of the device fabrication, especially in the metal trench contact. The SJ UMOS could overcome this by the orthogonal gate layout [20], but it is not suitable for the SGRSO device. For improving the electric field modulation effects, we analyse an AHP layout for the SGRSO device, as shown in Fig.…”

Section: Layout Structure and Operation Conceptmentioning

confidence: 99%

Advanced hexagonal layout design for split‐gate reduced surface field stepped oxide U‐groove metal–oxide–semiconductor field‐effect transistor

Wang

et al. 2015

IET Power Electronics

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Split-gate reduced surface field (RESURF) stepped oxide (SGRSO) device with advanced hexagonal p-pillar (AHP) layout is investigated using three-dimensional simulations. The AHP layout can improve the on-state characteristics while not increasing the process difficulty. The p-pillar under the source electrode enhances the RESURF effect to the n-drift region, so that the n-drift region doping concentration could be substantially increased and the breakdown voltage is not reduced. Based on the SGRSO device, the AHP layout modifies the electric field distribution in the n-drift region, and reduces the R SP as compared with the common hexagonal and mesa strip layout structures. The figure of merit of the AHP layout improves by 49.8% as compared with the other two types of layouts, and the AHP has superior characteristics within a wider N D range.

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“…For these issues, many process research studies and developments such as anisotropic epitaxial growth have been performed. [17][18][19] Consequently, SJ-MOSFETs using the trench filling method have attained a R ON 0A below the Si limit, [20][21][22][23][24][25][26][27] and the lowest reported R ON 0A of a fabricated SJ-MOSFET was 7.8 m³0cm 2 at a breakdown voltage of 685 V, which was lower than that of the SJ-MOSFET fabricated using the multistep epitaxy method. 24) Since SJ-MOSFETs can reduce the R D 0A markedly, it is also important to minimize the R CH 0A, R ACC 0A, and R JFET 0A.…”

Section: Introductionmentioning

confidence: 99%

Numerical analysis of specific on-resistance for trench gate superjunction MOSFETs

Ōnishi

Hashimoto

2015

Jpn. J. Appl. Phys.

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The numerical analysis results and theoretical limit of specific on-resistance (RON·A) for a parallel trench gate superjunction (SJ) MOSFET where a striped trench gate structure is parallel to a striped SJ structure and a perpendicular trench gate SJ-MOSFET where the striped trench gate structure is perpendicular to the striped SJ structure are presented. Analytical equations for relationships between breakdown voltage and RON·A are verified by device simulation and show good agreement with simulation results. When the MOSFET cell pitch is below half of the SJ pitch, in accordance with the numerical analysis results, the RON·A of the perpendicular SJ-MOSFET is smaller than that of the parallel SJ-MOSFET. This is due to the fact that the drift resistance including a current spreading effect and the channel resistance including a current narrowing effect in the perpendicular SJ-MOSFET are reduced by reducing the MOSFET cell pitch.

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Super Junction MOSFETs above 600V with Parallel Gate Structure Fabricated by Deep Trench Etching and Epitaxial Growth

Cited by 11 publications

References 5 publications

Effects of ion implantation process on defect distribution in SiC SJ-MOSFET

Effects of ion implantation process on defect distribution in SiC SJ-MOSFET

Advanced hexagonal layout design for split‐gate reduced surface field stepped oxide U‐groove metal–oxide–semiconductor field‐effect transistor

Numerical analysis of specific on-resistance for trench gate superjunction MOSFETs

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