Superconducting Shuttle-flux Shift Buffer for Race Logic

Bautista, Meriam Gay; Gonzalez-Guerrero, Patricia; Lyles, Darren

doi:10.1109/mwscas47672.2021.9531899

Cited by 4 publications

(2 citation statements)

References 24 publications

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“…For instance, for a control period duration of 150ps and a data pulse spacing of 15ps, each shift register has 150 15 = 10 stages of 15ps each. To reduce the JJ count as delay scales, we base our implementation on a flux-based shift register [37].…”

Section: A Router Overviewmentioning

confidence: 99%

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PaST-NoC: A Packet-Switched Superconducting Temporal NoC

Lyles

Gonzalez-Guerrero

Bautista

2023

IEEE Trans. Appl. Supercond.

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Temporal computing promises to mitigate the stringent area constraints and clock distribution overheads of traditional superconducting digital computing. To design a scalable, area-and power-efficient superconducting network on chip (NoC), we propose packet-switched superconducting temporal NoC (PaST-NoC). PaST-NoC operates its control path in the temporal domain using race logic (RL), combined with bufferless deflection flow control to minimize area. Packets encode their destination using RL and carry a collection of data pulses that the receiver can interpret as pulse trains, RL, serialized binary, or other formats. We demonstrate how to scale up PaST-NoC to arbitrary topologies based on 2×2 routers and 4×4 butterflies as building blocks. As we show, if data pulses are interpreted using RL, PaST-NoC outperforms state-of-the-art superconducting binary NoCs in throughput per area by as much as 5× for long packets.

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Section: A Router Overviewmentioning

confidence: 99%

“…Therefore, each shift register has E−P SP stages. We reduce area overhead by using a flux-based shift register [37].…”

Section: B Larger Topologies -8×8 2d Meshmentioning

confidence: 99%

PaST-NoC: A Packet-Switched Superconducting Temporal NoC

Lyles

Gonzalez-Guerrero

Bautista

2023

IEEE Trans. Appl. Supercond.

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An Area Efficient Superconducting Unary CNN Accelerator

Gonzalez-Guerrero,

Huch,

Patra

et al. 2023

2023 24th International Symposium on Quality Electronic Design (ISQED)

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Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications

Bautista

Gonzalez-Guerrero

Lyles

2023

IEEE Trans. Circuits Syst. I

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This paper presents a superconducting, magnetically-coupled, shuttle-flux shift register (SF-SR) that stores single flux quantum (SFQ) pulses. This shift register has a DC bias operating margin of ±34% at 10 GHz, with a power dissipation of 3.6µW and 38% fewer Josephson junctions (JJs) when scaled up to multiple stages compared to a data flip-flop (DFF) based shift register. The clock input is inductively coupled and is independent from the data input. We then present three applications for our SF-SR. In the first application, we add two non-destructive readout (NDRO) cells to construct a buffer that temporarily stores the temporal information of a series of race logic (RL) pulses. The second application is a pseudo-random number generator based on a linear function shift register (LFSR). The third application is N parallel SF-SRs that can act similar to a deserializer or instead can emulate a single SF-SR of N times higher clock frequency. These three applications motivate deep shift registers with many shifting intervals, which our SF-SR can implement with fewer JJs and lower power consumption compared to DFF-based shift registers.

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Superconducting Shuttle-flux Shift Buffer for Race Logic

Cited by 4 publications

References 24 publications

PaST-NoC: A Packet-Switched Superconducting Temporal NoC

PaST-NoC: A Packet-Switched Superconducting Temporal NoC

An Area Efficient Superconducting Unary CNN Accelerator

Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications

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