Superconductor Electronics Fabrication Process with MoNx Kinetic Inductors and Self-Shunted Josephson Junctions

Abstract

Recent progress in superconductor electronics fabrication has enabled single-flux-quantum (SFQ) digital circuits with close to one million Josephson junctions (JJs) on 1-cm 2 chips. Increasing the integration scale further is challenging because of the large area of SFQ logic cells, mainly determined by the area of resistively shunted Nb/AlOx-Al/Nb JJs and geometrical inductors utilizing multiple layers of Nb. To overcome these challenges, we are developing a fabrication process with self-shunted high-Jc JJs and compact thin-film MoNx kinetic inductors instead of geometrical inductors. We present fabrication details and properties of MoNx films with a wide range of Tc, including residual stress, electrical resistivity, critical current, and magnetic field penetration depth λ0. As kinetic inductors, we implemented Mo2N films with Tc about 8 K, λ0 about 0.51 μm, and inductance adjustable in the range from 2 to 8 pH/sq. We also present data on fabrication and electrical characterization of Nb-based self-shunted JJs with AlOx tunnel barriers and Jc = 0.6 mA/μm 2 , and with 10-nm thick Si1-xNbx barriers, with x from 0.03 to 0.15, fabricated on 200-mm wafers by cosputtering. We demonstrate that the electron transport mechanism in Si1-xNbx barriers at x < 0.08 is inelastic resonant tunneling via chains of multiple localized states. At larger x, their Josephson characteristics are strongly dependent on x and residual stress in Nb electrodes, and in general are inferior to AlOx tunnel barriers.

Superconducting Circuits without Inductors Based on Bistable Josephson Junctions

“…Theoretical estimation [12] of the maximum density of SFQ-based circuits utilizing geometrical inductance of wires corresponds to already achieved ∼ 10 7 JJ/cm 2 . A further decrease of the line width and spacing is problematic because of nearly exponential growth in mutual inductance and cross talk between the inductors [13]. The main approach to shrink the inductor is related to the utilization of kinetic inductance.…”

Considerations for Neuromorphic Supercomputing in Semiconducting and Superconducting Optoelectronic Hardware

“…The number of analog memory levels in the memory loop is determined by the inductance of the loop, which is easily set with the length of a wire. High-kinetic-inductance materials (Tolpygo et al, 2018 ) enable memory storage loops with over a thousand levels (10 bits) to be fabricated in an area of 5 μm × 5 μm.…”

Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS <italic>π</italic>-Junctions

“…In some experiments we also implemented Nb/Ni/Mo2N/Nb junctions, making a SFS'S-type structure, where a 35-nm overlay of superconducting Mo2N [4] was deposited on the Ni surface prior to the Nb top electrode deposition. This amorphous overlay was used to decrease the Josephson critical current density of magnetic junctions by modifying the interface with the Nb top electrode.…”

“…VER the past six years, our team has developed several nodes of the MIT Lincoln Laboratory (MIT LL) fabrication process for superconductor electronics (SCE), named SFQee, by progressively increasing the number of superconducting layers and decreasing the minimum linewidth [1]- [4]. This process development has been done within the framework of the IARPA C3 Program [5] for applications in energy efficient digital circuits based on different versions of pulsebased Single Flux Quantum (SFQ) logic.…”

“…Using this development approach, we have demonstrated circuits with close to one million JJs and circuit density over 1.3×10 6 JJ/cm 2 [7], [8]. To further increase the integration scale, we have recently introduced a fabrication process with self-shunted JJs and thin-film kinetic inductors [4], [9] in order to eliminate shunt resistors and reduce the area occupied by circuit inductors, the main impediments to increasing the integration scale of superconductor electronics [10]. The integration scale of SCE can be further increased by implementing multiple layers of active devices -Josephson junctions.…”