Superior Improvements in GIDL and Retention by Fluorine Implantation in Saddle-Fin Array Devices for Sub-40-nm DRAM Technology

Yang, Chia−Ming; Wang, Jer‐Chyi; Lee, Wei-Ping; Lee, Chien-Chi; Lin, Chih-Yang; Lee, Chung Yuan; Lin, Jui Che; Chen, Hsin-Huei; Hsiao, Chih‐Yang; Chang, Ruey-Dar; Lai, Chao−Sung

doi:10.1109/led.2013.2271274

Cited by 15 publications

References 15 publications

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Row hammer-induced D0 failure improvement in sub-20 nm DRAM using an air gap

Yoon,

Ahn

et al. 2024

Semicond. Sci. Technol.

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As the density of bit cells increases, reliability issue in state-of-the-art Dynamic Random Access Memory (DRAM) becomes critical. Row Hammer (RH) is one of the reliability issues in sub-20 nm DRAM product. This work proposes an air gap technique [i.e., placing an air gap beneath passing wordline (PWL)], to suppress the RH in sub-20 nm DRAM. Using 3D TCAD simulations, the electric field and Shockley-Read-Hall (SRH) recombination rate are investigated when the PWL is activated. And, when the PWL is deactivated, the leakage current toward the bitline is extracted, to investigate the impact of the air gap on RH. It turned out that a low-k dielectric material in the air gap can effectively help to reduce the electric field intensity near the interface between shallow-trench-isolation (STI) and silicon. The relatively weak electric field can prevent the flow of electrons that causes read/write errors through trap-assisted recombination. By adopting the air gap in STI, 82 % improvement was estimated in terms of alleviating RH.

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Row hammer-induced D0 failure improvement in sub-20 nm DRAM using an air gap

Yoon,

Ahn

et al. 2024

Semicond. Sci. Technol.

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Variation-aware analysis of buried-channel-array transistors (BCATs) in scaled DRAM: insights from 3D quasi-atomistic simulations

Yoon,

Lim,

Shin

2024

Semicond. Sci. Technol.

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As DRAM feature sizes continue to scale down, optimizing performance requires the evolution of architectures such as the buried-channel-array transistor (BCAT). Diminutive DRAM cell dimensions have increased susceptibility to variation, necessitating comprehensive simulations considering both systematic and random aspects. This study employs a three-dimensional quasi-atomistic model to implement surface random variations and investigates systematic structural variation induced by rounding between saddle-fin and source/drain regions. The impact on BCAT performance is analyzed using the standard deviation (SD) of output parameters, simultaneously simulating surface and structural aspects. Results show that increased surface roughness corresponds to increased SD, while alterations in structural variation, particularly channel and sidewall curvature, influence both mean and SD. Increased curvature leads to decreased threshold voltage and increased current levels. This simulation approach enables detailed estimation of variation distribution in BCATs, providing valuable insights for optimizing design and fabrication processes, ultimately enhancing DRAM performance and reliability. The findings highlight the importance of considering the interplay between surface and structural variations in advanced memory devices.

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Performance Improvement in DRAM Cell Using Novel Nitride/Metal Spacers Structure

Jung,

Min,

2024

IEEE Access

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Superior Improvements in GIDL and Retention by Fluorine Implantation in Saddle-Fin Array Devices for Sub-40-nm DRAM Technology

Cited by 15 publications

References 15 publications

Row hammer-induced D0 failure improvement in sub-20 nm DRAM using an air gap

Row hammer-induced D0 failure improvement in sub-20 nm DRAM using an air gap

Variation-aware analysis of buried-channel-array transistors (BCATs) in scaled DRAM: insights from 3D quasi-atomistic simulations

Performance Improvement in DRAM Cell Using Novel Nitride/Metal Spacers Structure

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