Superscalar Coprocessor for High-Speed Curve-Based Cryptography

Sakiyama, Kazuo; Batina, Lejla; Preneel, Bart; Verbauwhede, Ingrid

doi:10.1007/11894063_33

Cited by 21 publications

(15 citation statements)

References 25 publications

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“…They both use explicit formulae, and the designs are much smaller than other implementations. The HECC coprocessor presented in [32] uses projective coordinates and a superscalar architecture. Different number of digit-serial (w¼12) multipliers are used for different configurations.…”

Section: Results and Comparisonmentioning

confidence: 99%

“…Different number of digit-serial (w¼12) multipliers are used for different configurations. Our coprocessor, using one unified multiplier/inverter, is faster than the one of [32] using three multipliers.…”

Section: Results and Comparisonmentioning

confidence: 99%

“…We choose w M ¼14 such that the area meets our constraints, i.e., the overall area should be smaller than the smallest known implementation ( [32] in Table 2). We then adjust w I and measure the performance of the UMI on a Xilinx XC2V4000 FPGA.…”

Section: Type-i Hecc Processormentioning

confidence: 99%

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Design and design methods for unified multiplier and inverter and its application for HECC

2011

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a b s t r a c tThis paper describes two novel architectures for a unified multiplier and inverter (UMI) in GF(2 m ): the UMI merges multiplier and inverter into one unified data-path. As such, the area of the data-path is reduced. We present two options for hyperelliptic curve cryptography (HECC) using UMIs: an FPGAbased high-performance implementation (Type-I) and an ASIC-based lightweight implementation (Type-II). The use of a UMI combined with affine coordinates brings a smaller data-path, smaller memory and faster scalar multiplication.Both implementations use curves defined by h(x) ¼x and f ðxÞ ¼The high throughput version uses 2316 slices and 2016 bits of block RAM on a Xilinx Virtex-II FPGA, and finishes one scalar multiplication in 311 ms. The lightweight version uses only 14.5 kGates, and one scalar multiplication takes 450 ms.

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Section: Results and Comparisonmentioning

confidence: 99%

Section: Results and Comparisonmentioning

confidence: 99%

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Design and design methods for unified multiplier and inverter and its application for HECC

2011

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“…Yao et al [40] followed the idea of using RNS to design a high-speed ECC co-processor for pairings. Sakiyama et al [35] proposed a superscalar coprocessor that could deal with three different curve-based cryptosystems, all in characteristic 2 fields. Varchola et al [38] designed a processor-like architecture, with instruction set and decoder, on top of which they implemented ECC.…”

Section: Introductionmentioning

confidence: 99%

Implementing Complete Formulas on Weierstrass Curves in Hardware

Massolino¹,

Renes²,

Batina³

2016

Security, Privacy, and Applied Cryptography Engineering

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Abstract. This work revisits the recent complete addition formulas for prime order elliptic curves of Renes, Costello and Batina in light of parallelization. We introduce the first hardware implementation of the new formulas on an FPGA based on three arithmetic units performing Montgomery multiplication. Our results are competitive with current literature and show the potential of the new complete formulas in hardware design. Furthermore, we present algorithms to compute the formulas using anywhere between two and six processors, using the minimum number of parallel field multiplications.

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“…Recently significantly fast implementations are proposed by [26,27]. Our previous work [28] employs a superscalar architecture to exploit ILP in ECC over GF(2 n ). The cryptoprocessor is scalable in field size and programmable for various EC scalar multiplication algorithms.…”

Section: Introductionmentioning

confidence: 99%

High-performance Public-key Cryptoprocessor for Wireless Mobile Applications

et al. 2007

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We present a high-speed public-key cryptoprocessor that exploits three-level parallelism in Elliptic Curve Cryptography (ECC) over GF(2 n ). The proposed cryptoprocessor employs a Parallelized Modular Arithmetic Logic Unit (P-MALU) that exploits two types of different parallelism for accelerating modular operations. The sequence of scalar multiplications is also accelerated by exploiting Instruction-Level Parallelism (ILP) and processing multiple P-MALU instructions in parallel. The system is programmable and hence independent of the type of the elliptic curves and scalar multiplication algorithms. The synthesis results show that scalar multiplication of ECC over GF(2 163 ) on a generic curve can be computed in 20 and 16 μs respectively for the binary NAF (Non-Adjacent Form) and the Montgomery method. The performance can be accelerated furthermore on a Koblitz curve and reach scalar multiplication of 12 μs with the TNAF (τ -adic NAF) method. This fast performance allows us to perform over 80,000 scalar multiplications per second and to enhance security in wireless mobile applications.

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Superscalar Coprocessor for High-Speed Curve-Based Cryptography

Cited by 21 publications

References 25 publications

Design and design methods for unified multiplier and inverter and its application for HECC

Design and design methods for unified multiplier and inverter and its application for HECC

Implementing Complete Formulas on Weierstrass Curves in Hardware

High-performance Public-key Cryptoprocessor for Wireless Mobile Applications

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