Superscalar instruction issue

Sima, D.

doi:10.1109/40.621211

Cited by 14 publications

(5 citation statements)

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“…1) The Principle of the Direct Issue Scheme: For issuing multiple instructions per cycle early superscalars typically used some variants of the direct issue scheme in conjunction with a simple branch speculation [52]. Direct issue means that after decoding, executable instructions are issued immediately to the execution units (EUs), as shown in Figure 15.…”

Section: The Direct Issue Scheme and The Resulting Issue Bottleneckmentioning

confidence: 99%

“…Dependent instructions remain in the window. Variants of this scheme differ on two aspects: how the window is filled and how dependencies are handled [49], [52].…”

Section: The Direct Issue Scheme and The Resulting Issue Bottleneckmentioning

confidence: 99%

“…Issue parallelism, also known as superscalar instruction issue [51] [5], [52], refers to the issuing of multiple decoded instructions per clock cycle by the instruction fetch/decode part of the microarchitecture for further processing. The maximum number of instructions issued per clock cycle is called the issue rate (n i ).…”

Section: A Introduction Of Issue Parallelismmentioning

confidence: 99%

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Decisive aspects in the evolution of microprocessors

Sima

2004

Proc. IEEE

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The incessant demand for higher performance has provoked a dramatic evolution of the microarchitecture of high performance microprocessors. In this paper we focus on major architectural developments which were introduced for a more effective utilization of instruction level parallelism (ILP) in commercial, performance oriented microprocessors. We show that designers increased the throughput of the microarchitecture at the instruction level basically by the subsequent introduction of temporal, issue and intra-instruction parallelism in such a way that exploiting parallelism along one dimension gave rise to the introduction of parallelism along another dimension. Moreover, the debut of each basic technique used to introduce parallel operation along a certain dimension inevitably called for the introduction of further innovative techniques to avoid processing bottlenecks that arise. Pertinent relationships constitute an underlying logical framework for the fascinating evolution of microarchitectures, which is presented in our paper.

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Section: The Direct Issue Scheme and The Resulting Issue Bottleneckmentioning

confidence: 99%

“…Dependent instructions remain in the window. Variants of this scheme differ on two aspects: how the window is filled and how dependencies are handled [49], [52].…”

Section: The Direct Issue Scheme and The Resulting Issue Bottleneckmentioning

confidence: 99%

Section: A Introduction Of Issue Parallelismmentioning

confidence: 99%

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Decisive aspects in the evolution of microprocessors

Sima

2004

Proc. IEEE

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“…Figure 1 shows a block diagram of the issue logic associated to one entry of the issue queue. Whether the issue queue stores operand values or just operand tags affects the design, as Sima 1 and others discuss. The selection process identifies instructions whose source operands are ready and whose required resources are available, and then issues them for execution.…”

Section: Basic Cam-based Approachesmentioning

confidence: 99%

Power- and complexity-aware issue queue designs

2003

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50Current microprocessors are designed to execute instructions in parallel and out of order. In general, superscalar processors fetch instructions in order. After the branch prediction logic determines whether a branch is taken (or not) and its target address, the processor decodes the instructions and renames the register operands, removing name dependences introduced by the compiler. Because processors generally have more physical than logical registers, multiple instructions with the same logical destination can be in flight simultaneously. The renamed instructions then go into the issue queue where they wait until their operands are ready and their required resources are available. At the same time, instructions go into the reorder buffer, where they remain until they commit their results. When an instruction executes, the wakeup logic notifies dependent instructions that the corresponding operand is available. Finally, instructions commit their results in program order.This article focuses on the design of the logic that stores the instructions waiting for execution, as well as the logic associated with identifying whether operands are ready and selecting the instructions that start execution every cycle. All these components are part of the issue logic. Issue logic is one of the most complex parts of superscalar processors, one of the largest consumers of energy, and one of the main sites of power density. Its design is therefore critical for performance.Researchers have used a variety of schemes to implement the issue queue. In particular, several recent proposals have attempted to reduce the issue logic's complexity and power. To the best of our knowledge, this article is the first attempt to perform a comprehensive and thorough survey of the issue logic design space. Basic CAM-based approachesOne of the most common ways to implement the issue logic is based on contentaddressable memory (CAM) and RAM array structures. These structures can store several instructions, but generally fewer than the total number of in-flight instructions. Each entry contains an instruction that has not been issued or has been issued speculatively but not yet validated and thus might need to be reexecuted.In general, entries use RAM cells to store operations, destination operands, and flags indicating whether source operands are ready while CAM cells store source operand identifiers-referred to here as tags. Overall, the issue logic's main source of complexity and power dissipation is the many tag comparisons it must perform every cycle. Researchers have proposed several approaches to improve the issue logic's power efficiency. We classify these approaches into two groups:• static approaches, which use fixed structures, and • dynamic approaches, which dynamically adapt some structures according to the properties of the executed code.Orthogonally, researchers have proposed several more efficient circuit designs, but they don't reduce the inherent complexity. Dynamic approachesOne approach to reducing the power dissipation is b...

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“…The basic technique used to remove an issue bottleneck is instruction shelving, also known as dynamic instruction issue. 3,35,45 Shelving presumes the availability of dedicated buffers, called shelving buffers, in front of the execution units. The processor first issues instructions into available shelving buffers without checking for data or control dependencies, or for busy execution units.…”

Section: Instruction Shelving Principlementioning

confidence: 99%

The design space of register renaming techniques

Sima¹

2000

IEEE Micro

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70Register renaming is a technique to remove false data dependencies-write after read (WAR) and write after write (WAW)-that occur in straight line code between register operands of subsequent instructions. [1][2][3] By eliminating related precedence requirements in the execution sequence of the instructions, renaming increases the average number of instructions that are available for parallel execution per cycle. This results in increased IPC (number of instructions executed per cycle).The identification and exploration of the design space of register-renaming lead to a comprehensive understanding of this intricate technique. As this article shows, the design space of register renaming is spanned by four main dimensions: the scope of register renaming, the layout of the rename buffers, the method of register mapping, and the rename rate. Relevant aspects of the design space give rise to eight basic alternatives for register-renaming. In addition, the kind of operand fetch policy significantly affects how the processor carries out the rename process, which duplicates the eight basic alternatives to 16 possible implementation schemes. The article indicates which basic implementation scheme is used in relevant superscalar processors.As register renaming is usually implemented in conjunction with shelving, the underlying microarchitecture is assumed to employ shelving. (See the "Instruction shelving principle" box for a discussion of this technique.) Register renamingThe principle of register renaming is straightforward. If the processor encounters an instruction that addresses a destination register, it temporarily writes the instruction's result into a dynamically allocated rename buffer rather than into the specified destination register. For instance, in the case of the following WAR dependency:the destination register of i2 (r2) is renamed, say to r33. Then, instruction i2 becomesIts result is written into r33 instead of into r2. This resolves the previous WAR dependency between i1 and i2. In subsequent instructions, however, references to source registers must be redirected to the rename buffers allocated to them as long as this renaming remains valid. 3A precursor to register renaming was introduced for floating-point instructions in 1967 by Tomasulo in the IBM 360/91, 4 a scalar supercomputer of that time that pioneered both pipelining and shelving (dynamic instruction issue). The 360/91 renamed floating-point registers to preserve the logical consistency of the program execution rather than to remove false data dependencies.

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Superscalar instruction issue

Cited by 14 publications

References 33 publications

Decisive aspects in the evolution of microprocessors

Decisive aspects in the evolution of microprocessors

Power- and complexity-aware issue queue designs

The design space of register renaming techniques

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