Supply voltage degradation aware analytical placement

Kahng, Andrew B.; Liu, Bao; Wang, Qinke

doi:10.1109/iccd.2005.101

Cited by 15 publications

(9 citation statements)

References 28 publications

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“…The current upper bounds can guarantee the circuit operates correctly even under the worst-case scenarios. Consequently, the peak current modeling is widely used in the literature [39][40][41][42][43][44] for voltage drop optimization. Because we consider soft blocks which do not have the exact placement of the standard cells at the floorplanning stage, our current model uses the peak current function, which is based on worst-case scenarios and takes account of area, switching activity, and current density simultaneously, to determine the load current.…”

Section: Current Source Modelingmentioning

confidence: 99%

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Chu

Xia

Wang

et al. 2015

Circuit Theory & Apps

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Multi-voltage techniques are being developed to improve power savings by providing lower supply voltages for noncritical blocks under the performance constraint. However, the resulted lower voltage drop noise margin brings serious obstacles in power/ground (P/G) network design of the wire-bonding package. For voltage drop optimization, both block and power pad positions are important factors that need to be considered. Traditional multi-voltage floorplanning methods use rough estimation to evaluate the P/G network resource without considering the locations of power pads. To remedy this deficiency, in this paper, an efficient voltage drops aware power pad assignment (PPA) method is proposed, and it is further integrated into a floorplanning algorithm. We first present a fast PPA method for each power domain by the spring model. Then, to evaluate voltage drops during floorplanning iterations, the weighted distance from the blocks to the power pads is adopted as an optimization objective instead of time-consuming matrix computation. Experimental results on Gigascale System Research Center (GSRC) benchmark circuits indicate that the proposed method generates an optimized placement of power pads and floorplanning of blocks with high efficiency.decoupling capacitors configuration to alleviate the power delivery noise [12,13]. However, those techniques are implemented only when the floorplan or placement is ready. With exploding design complexity, it is necessary to consider voltage drop issues in the early design cycle [14][15][16][17]. Once the voltage drops aware floorplan is obtained, the detailed P/G network design can be performed in the subsequent placement and routing stages that consider Steiner tree construction and electromigration issues [18,19].It is reported that 5% of voltage decrease may cause the circuit performance slowdown up to 15% or more [20]. Hence, designers typically limit the voltage drops within 10% of the supply voltage to guarantee faultless operation [21]. Lower supply voltage indicates that lower noise margins or smaller voltage drops are permitted on the P/G network [22]. For instance, 1.5-V supply voltages permit 150-mV voltage drop while 1.0-V supply voltages only allow 100-mV voltage drop. Compared with single-voltage SoC, the voltage drop constraints present more challenges for the P/G network design of the multi-voltage SoC. First, from a low-power perspective, a VI with a larger area and a lower supply voltage is preferred during the VI generation process. However, the permitted ultra-low voltage drops make the P/G network hard to design. Second, power pads are located at the periphery of the chip for wire-bonding package. Locations of power pads affect both the timing and voltage drops [23]. Although multiple power pads for each VI can leverage the voltage drops, it may not be practical because the power pads must compete with other signal I/Os under the limited pad resource. Thus, it is vital to consider voltage drops in P/G network design for multi-voltage SoC. Related workConsid...

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Section: Current Source Modelingmentioning

confidence: 99%

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Chu

Xia

Wang

et al. 2015

Circuit Theory & Apps

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“…In [5] we present a supply voltage degradation-aware analytical placement method which relocates cells to reduce supply voltage degradation. We represent supply voltage degradation at an observed power supply node as function of supply currents and effective resistances in a DC power network, and integrate supply voltage degradation into the APlace framework.…”

Section: Recent Applicationsmentioning

confidence: 99%

“…In other recent work, we have successfully applied the APlace framework to perform supply voltage degradationaware placement [5] and lens aberration-aware timing-driven placement [6]. We briefly describe each of these adaptations in this paper.…”

Section: Introductionmentioning

confidence: 98%

A faster implementation of APlace

Kahng

Wang

2006

Proceedings of the 2006 International Symposium on Physical Design

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APlace is a high quality, scalable analytical placer. This paper describes our recent efforts to improve APlace for speed and scalability. We explore various wirelength and density approximation functions. We speed up the placer using a hybrid usage of wirelength and density approximations during the course of multi-level placement, and obtain 2-2.5 times speedup of global placement on the IBM ISPD04 and ISPD05 benchmarks. Recent applications of the APlace framework to supply voltage degradation-aware placement and lens aberration-aware timing-driven placement are also briefly described.

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“…These hotspots should be resolved at the signoff stage to avoid timing degradation and functional failure. Placing cells to minimize static IR-drop has been proven to be NP-hard [4]. The dynamic IR-drop optimization problem is more complicated due to the time-variant property.…”

Section: Introductionmentioning

confidence: 99%