Supporting Speculative Multithreading on Simultaneous Multithreaded Processors

Packirisamy, Venkatesan; Wang, Shengyue; Zhai, Antonia; Hsu, Wei-Chung; Yew, Pen-Chung

doi:10.1007/11945918_19

Cited by 10 publications

(8 citation statements)

References 16 publications

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“…A study by Packirisamy et al [2006] looks at ways for supporting two or four speculative threads on an SMT core. Commits in the design are slow and complex involving write-backs and merging of lines from multiple contexts.…”

Section: Related Workmentioning

confidence: 99%

SCIN-cache

Negi

Titos-Gil

2013

ACM Trans. Archit. Code Optim.

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This article describes cache designs for efficiently supporting speculative techniques like transactional memory on chip multiprocessors with multithreaded cores. On-demand allocation and prompt freeing of speculative cache space in the design reduces the burden on nonspeculative execution. Quick access to both clean and speculative versions of data for multiple contexts provides flexibility and greater design freedom to HTM architects. Performance analysis shows the designs stand up well against other HTM design proposals, with potential performance gains in high contention applications with small transactions.

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Section: Related Workmentioning

confidence: 99%

SCIN-cache

Negi

Titos-Gil

2013

ACM Trans. Archit. Code Optim.

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“…Each first-level cache line is further extended with bits to indicate whether it is speculatively loaded or modified, and if so, by which thread(s). The rest of the hardware support and implementation details can be found in Packirisamy et al [2006]. …”

Section: Architectural Support For Speculationmentioning

confidence: 99%

The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution

Luo

Hsu

Zhai

2013

ACM Trans. Archit. Code Optim.

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With the emergence of multicore processors, various aggressive execution models have been proposed to exploit fine-grained thread-level parallelism, taking advantage of the fast on-chip interconnection communication. However, the aggressive nature of these execution models often leads to excessive energy consumption incommensurate to execution time reduction. In the context of Thread-Level Speculation, we demonstrated that on a same-ISA heterogeneous multicore system, by dynamically deciding how on-chip resources are utilized, speculative threads can achieve performance gain in an energy-efficient way.Through a systematic design space exploration, we built a multicore architecture that integrates heterogeneous components of processing cores and first-level caches. To cope with processor reconfiguration overheads, we introduced runtime mechanisms to mitigate their impacts. To match program execution with the most energy-efficient processor configuration, the system was equipped with a dynamic resource allocation scheme that characterizes program behaviors using novel processor counters.We evaluated the proposed heterogeneous system with a diverse set of benchmark programs from SPEC CPU2000 and CPU20006 suites. Compared to the most efficient homogeneous TLS implementation, we achieved similar performance but consumed 18% less energy. Compared to the most efficient homogeneous uniprocessor running sequential programs, we improved performance by 29% and reduced energy consumption by 3.6%, which is a 42% improvement in energy-delay-squared product.

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“…Regarding DMT, IMT led to better results than DMT thanks to prediction enhancements, and also to the elimination of the selective recovering from misspeculations that required several searches. [Packirisamy et al 2006] extended the SMT architecture to support TLS with the use of a modified L1 data cache. The new cache scheme consisted of the addition of a pointer to the thread which stored a value in the cache, and some speculative bits to save the loads and stores performed to variables.…”

Section: Dynamic Multithreading Processor (Dmp)mentioning

confidence: 99%