Suppression of tunneling leakage current in junctionless nanowire transistors

Abstract

In this paper, the characteristics of tunneling leakage current for the dual-material gate junctionless nanowire transistor (DMG-JNT) are investigated by three-dimensional numerical simulations and compared with conventional junctionless nanowire transistor (JNT). The suppression of the tunneling leakage current on the JNT by introducing an energy band step with the DMG structure is verified and presented for the first time. The effects of channel length on the DMG-JNT and the JNT are also studied. Results showed that the tunneling leakage current of the DMG-JNT is two orders smaller than that of the JNT, and further, the DMG-JNT exhibits superior scaling capability. Two key design parameters of the DMG-JNT, control gate ratio (Ra) and work function difference (δW), have been optimized and the optimal ranges of Ra and δW are pointed out.

Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

“…However, the inclusion of an oppositely doped core widens this tunneling width and enhances source to channel barrier height that cumulatively decreases I OFF in I-JL-NWFET [11]. Additionally, the employment of two dissimilar gate work functions in the DMG structure results in an abrupt transition, further amplifying the tunneling width of I-JL-NWFET [13].…”

“…Moreover, the lower gate work function toward the drain reduces the magnitude of the drain-channel electric field experienced by electrons. As a result, the device is less susceptible to hot carrier-induced degradation and SCEs [13][14][15]. Additionally, the inclusion of the high-k material in the gate sidewall spacer region further alleviates the Lateral Band-to-Band Tunneling (L-BTBT) of electrons in the OFF-state [16,17].…”

Oppositely-Doped Core-Shell Junctionless Nanowire FET: Design and Investigation

“…Numerous studies in the literature have proposed the utilization of Dual Material Gate (DMG) to enhance carrier mobility, ON-state (V GS = 1 V, V DS = 1 V) current (I ON ), and transconductance in comparison to Single Material Gate (SMG) JLT by carefully adjusting the channel potential and electric field distributions along the channel length. [28][29][30][31] The DMG architecture involves two gate metals, where the work function of gate metal 1 (M1) is higher than that of gate metal 2 (M2). Additionally, researchers have extensively investigated the incorporation of a high-dielectric constant (k) spacer on both sides of the gate to further enhance immunity against SCEs.…”

Triple-gate junctionless MOSFETs

“…As mentioned, the on-state current of JLTs is lower than that of the inversion mode devices [46] and therefore, the off-state leakage current is of great significance for these devices. Several works are referred in previous literature regarding compact models for the drain current in the on-state region [59][60][61][62] and leakage current investigation in the off-state region of JNTs [63][64][65][66][67][68]. In particular, the effect of longitudinal band-to-band tunneling (BTBT) from the channel to the drain in the off-state range of operation of silicon-on-insulator (SOI) and bulk planar JLTs [63], vertically stacked nanowire JNTs [64] and dual-material gate nanowire JLTs [65,66] have been studied with numerical simulations to optimize the on/off current ratio.…”

“…Several works are referred in previous literature regarding compact models for the drain current in the on-state region [59][60][61][62] and leakage current investigation in the off-state region of JNTs [63][64][65][66][67][68]. In particular, the effect of longitudinal band-to-band tunneling (BTBT) from the channel to the drain in the off-state range of operation of silicon-on-insulator (SOI) and bulk planar JLTs [63], vertically stacked nanowire JNTs [64] and dual-material gate nanowire JLTs [65,66] have been studied with numerical simulations to optimize the on/off current ratio. A number of analytical surface potential and charge-based models have been reported in the literature for long-channel JL double-gate (DG) MOSFETs [69]- [74].…”