Surface Defect Passivation of Silicon Micropillars

Abstract

Reactive ion etching (RIE) used to fabricate high‐aspect‐ratio (HAR) nano/microstructures is known to damage semiconductor surfaces which enhances surface recombination and limits the conversion efficiency of nanostructured solar cells. Here, defect passivation of ultrathin Al2O3‐coated Si micropillars (MPs) using different surface pretreatment steps is reported. Effects on interface state density are quantified by means of electrochemical impedance spectroscopy which is used to extract quantitative capacitance–voltage and conductance–voltage characteristics from HAR dielectric–semiconductor structures which would otherwise suffer from high gate leakage currents if tested using solid‐state metal–insulator–semiconductor structures. High‐temperature thermal oxidation to form a sacrificial oxide on RIE‐fabricated Si MPs, followed by atomic layer deposition of 4 nm thick Al2O3 after removal of the sacrificial layer produces an interface trap density (D it) as low as 1.5 × 1011 cm−2 eV−1 at the mid‐gap energy of silicon. However, a greatly reduced mid‐gap D it (2 × 1011 cm−2 eV−1) is possible even with a simple air annealing procedure having a maximum temperature of 400 °C.

Link between Gas Phase Reaction Chemistry and the Electronic Conductivity of Atomic Layer Deposited Titanium Oxide Thin Films

“…For example, ALD has become an indispensable tool in nanoelectronics to form the gate dielectric layers at the heart of metal oxide semiconductor field effect transistors. , The availability of a large range of molecular precursors enables development of ALD processes for deposition of a wide array of metal oxides, nitrides, phosphides, sulfides, carbides, and an increasing number of elemental metals. ALD has become increasingly important in corrosion protection, , synthesis of catalysts, , battery electrode coatings, − and in surface passivation of solar cells. − …”

Fabrication of Nanostructured GaAs/AlGaAs Waveguide for Low-Density Polariton Condensation from a Bound State in the Continuum

“…Surface recombination can be minimized through oxide removal and surface passivation, achievable through etching at sufficiently low ion energy to remain in the ion-assisted chemical etching regime [41][42][43]. For this reason, the sample was immersed in a hydrochloric acid bath to remove the surface oxide, and then 8nm of Al 2 O 3 were deposited via atomic layer deposition [44][45][46][47] (ALD) at 300°C [48] (see Supplementary Material). The observed emission intensities in the three cases along with the gap size and excitonic fraction are shown in Fig.…”

“…The sample was placed in a Oxford FlexAl-Plasma Enhanced Atomic Layer Deposition and kept for 10 minutes at a temperature of 300°C before starting the deposition [48]. The alumina layer was conformally grown all over the sample to reduce the nonradiative recombination rate at the GaAs grating sidewalls [44,46,47]. The SEM image in Fig.…”

Reducing Conductivity Variability in Si Nanowires via Surface Passivation for Nanoelectronics

“…(ii) Increase in Conductivity with Passivation : A 3-orders-of-magnitude increase in conductivity was observed with surface passivation (Figure ). On the basis of literature values, , we assume passivation induces a change in interface-state density from ∼10 12 to ∼10 11 cm –2 . For a dopant concentration of 2 × 10 17 cm –3 , an order-of-magnitude decrease in D it from 10 12 to 10 11 cm –2 can translate to a 4-orders-of-magnitude change in the conductivity of the nanowire (carrier concentration change from ∼1 × 10 12 to 5 × 10 16 cm –3 ), which is consistent with our results.…”

“…Several studies show that the Al 2 O 3 dielectric layer can reduce the surface recombination rate and increase the minority carrier lifetime of Si nanowire and micropillar solar cells. − Garnett et al reported the interface trap density of the Si nanowire/Al 2 O 3 ALD interface to be comparable to the high quality Si/SiO 2 interface, 4 × 10 11 eV –1 cm –2 at midgap, as extracted from the C–V response of Si nanowire field-effect transistors . A recent report shows that Al 2 O 3 combined with pre-ALD annealing in air can significantly reduce the interface trap density in Si micropillars to 1.5 × 10 11 eV –1 cm –2 at midgap and increase the minority carrier lifetime . However, these previous studies only report on the performance of an individual or handful devices.…”