1984
DOI: 10.1109/t-ed.1984.21515
|View full text |Cite
|
Sign up to set email alerts
|

Surface induced latchup in VLSI CMOS circuits

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
1
0

Year Published

1986
1986
1995
1995

Publication Types

Select...
5
1

Relationship

0
6

Authors

Journals

citations
Cited by 29 publications
(1 citation statement)
references
References 0 publications
0
1
0
Order By: Relevance
“…For future VLSI/ULSI integrated circuits thin, lightly doped epitaxial layers grown on highly conducting substrates will be required to minimize CMOS latch-up and improve radiation hardness. Recent investigations have shown that the closer the highly conductive substrate is placed to the active device region (meaning of course the thinner the epitaxial layer) the more resistant to latch-up the devices fabricated on this structure are (1). Technologies such as plasma-assisted epitaxy (2) and low temperature, low pressure epitaxy (3) are being aggressively pursued to grow these thin epitaxial layers by minimizing the problems of gas phase autodoping and solid-state outdiffusion.…”
mentioning
confidence: 99%
“…For future VLSI/ULSI integrated circuits thin, lightly doped epitaxial layers grown on highly conducting substrates will be required to minimize CMOS latch-up and improve radiation hardness. Recent investigations have shown that the closer the highly conductive substrate is placed to the active device region (meaning of course the thinner the epitaxial layer) the more resistant to latch-up the devices fabricated on this structure are (1). Technologies such as plasma-assisted epitaxy (2) and low temperature, low pressure epitaxy (3) are being aggressively pursued to grow these thin epitaxial layers by minimizing the problems of gas phase autodoping and solid-state outdiffusion.…”
mentioning
confidence: 99%