Surface-Potential-Based Drain Current Model for Polycrystalline Silicon Thin-Film Transistors

Tsuji, Hiroshi; Kuzuoka, Takashi; Kishida, Yuji; Shimizu, Yoshiyuki; Kirihara, Masaharu; Kamakura, Yoshinari; Morifuji, Masato; Shimizu, Y.; Miyano, S.; Taniguchi, Kenji

doi:10.1143/jjap.47.7798

Cited by 12 publications

(2 citation statements)

References 14 publications

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“…Thus far, several compact models of poly-Si TFTs have been proposed for circuit simulation. [28][29][30] They are used for simulation in the practical design process. Thus, objective TFT devices are assumed to show good performance in terms of electrical properties.…”

Section: Remarks On the Conventional Compact Modelsmentioning

confidence: 99%

Pinch-Off Voltage Lowering in Polycrystalline Silicon Thin-Film Transistors

Ikeda

Sano

2011

Jpn. J. Appl. Phys.

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Pinch-off voltage (V p) lowering phenomenon in the output characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) is reported and investigated by measurement and device simulation. As the trap density increases, the observed V p becomes smaller than the ideal V p while maintaining a linear relationship with the gate–source voltage (V gs). The device simulation analysis revealed two mechanisms for V p lowering. One is current saturation due to the increase in onset gate–drain voltage (V gd), causing the drain region to become highly resistive, which originates from the gradual increase in surface potential with V gs. This is interpreted as an expansion of the conventional pinch-off concept. The other is the current limitation, controlled by grain boundary (GB) and intragrain conductance at the drain edge, which is peculiar to poly-Si TFTs. On the basis of the above analysis, a GB-conductance-limited carrier transport model is proposed. Its good agreement with the measurements suggests the suitability of this model for describing V p lowering.

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Section: Remarks On the Conventional Compact Modelsmentioning

confidence: 99%

Pinch-Off Voltage Lowering in Polycrystalline Silicon Thin-Film Transistors

Ikeda

Sano

2011

Jpn. J. Appl. Phys.

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“…As is well known from Ref. [6], the energy-distributed acceptorlike density of states (DOS) of polysilicon can be accurately modeled by the sum of two exponential functions, accounting for tail states as well as deep states. In addition, the models OE10;11 used a regional approach to solve the surface potential, where different sets of equations were applied for different dominant terms and neglected other contributions.…”

Section: Introductionmentioning

confidence: 99%

Explicit solution of channel potential and drain current model in symmetric double-gate polysilicon TFTs

Ma¹,

Deng²,

Huang

2014

J. Semicond.

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A physical and explicit surface potential model for undoped symmetric double-gate polysilicon thinfilm transistors has been derived based on an effective charge density approach of Poisson's equation with both exponential deep and tail state terms included. The proposed surface potential calculation is single-piece and eliminates the regional approach. Model predictions are compared to numerical simulations with close agreement, having absolute error in the millivolt range. Furthermore, expressions of the drain current are given for a wide range of operation regions, which have been justified by thorough comparisons with experimental data.

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