2021
DOI: 10.1016/j.mssp.2021.106153
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Surface residual stress in amorphous SiO2 insulating layer on Si substrate near a Cu through-silicon via (TSV) investigated by nanoindentation

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Cited by 15 publications
(6 citation statements)
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“…The residual stress inner SiO 2 is 84.75 MPa, under thermal cycling, which is less than the stress as fabricated at 225.61 MPa and the annealed stress at 281.15 MPa. The residual stress of inner Si, as fabricated, is 320 MPa, which is similar to the stress measured by the nanoindentation test in [17]. The residual stress in Si is mainly influenced by the stress in TSV-Cu.…”
Section: Residual Stress Distributionsupporting
confidence: 75%
See 1 more Smart Citation
“…The residual stress inner SiO 2 is 84.75 MPa, under thermal cycling, which is less than the stress as fabricated at 225.61 MPa and the annealed stress at 281.15 MPa. The residual stress of inner Si, as fabricated, is 320 MPa, which is similar to the stress measured by the nanoindentation test in [17]. The residual stress in Si is mainly influenced by the stress in TSV-Cu.…”
Section: Residual Stress Distributionsupporting
confidence: 75%
“…However, the local residual stress of TSV-Cu cannot be obtained using the wafer curvature method. In addition, the characterization of local residual stress on TSV-Cu surface can be accomplished via Raman spectroscopy, X-ray microdiffraction, secondharmonic spectroscopy, and the nanoindentation test [12][13][14][15][16][17][18]. Nevertheless, the above characterization methods have strict requirements regarding the material surface.…”
Section: Introductionmentioning
confidence: 99%
“…As the O2 flux increases, the hardness of the coatings decreases, causing a reduction in the scratch resistance. It should be noted that the hardness of the Si/O-DLC coating with a small amount of O doping is comparable to that of SiO 2 , which is widely used in insulating materials [28]. However, as the O 2 flux increases from 2 sccm to 6 sccm, the hardness and elastic modulus of the Si/O-DLC coatings decrease from approximately 10 GPa to 6.6 GPa and from approximately 110 GPa to 58.5 GPa, respectively.…”
Section: Resultsmentioning
confidence: 99%
“…The hardness and elastic modulus of the pure Si-DLC coating (the O2 flux = 0 sccm) are approximately 10 GPa and 151 GPa, respectively. As a small amount of O is added (the O2 flux = 2 sccm), the hardness of the coatings is almost maintained at approximately 10 GPa.It should be noted that the hardness of the Si/O-DLC coating with a small amount of O doping is comparable to that of SiO2, which is widely used in insulating materials[28]. However, as the O2 flux increases from 2 sccm to 6 sccm, the hardness and elastic modulus of the Si/O-DLC coatings decrease from approximately 10 GPa to 6.6 GPa and from approximately 110 GPa to 58.5 GPa, respectively.…”
mentioning
confidence: 96%
“…Through Silicon Via (TSV) is a through hole in the z-axis direction on a silicon substrate, and the conductive material copper is filled in the through hole, thereby realizing the interconnection between different functional chips. 1,2 Compared with the previous technology, TSV can make the chips have the highest stacking density in the threedimensional direction, the shortest interconnection between chips, and the smallest external size, thereby greatly improving the signal transmission speed of the chip and reducing the power consumption. It is the most advanced electronic packaging technology.…”
mentioning
confidence: 99%