Surface roughness and dislocation distribution in compositionally graded relaxed SiGe buffer layer with inserted-strained Si layers

Abstract

We investigate the surface roughness and dislocation distribution of compositionally graded relaxed SiGe buffer layers by inserting two tensile-strained Si layers. The 20nm thick strained Si layers, less than the critical thickness for dislocation formation, are inserted at 10 and 20% Ge content regions of the 1μm thick graded SiGe layer with a final Ge content of 30%. The surface immediately after growing the second strained Si layer on SiGe with 20% Ge content is found to be flat with about 1.1nm root-mean-square roughness. However, the crosshatched surface with the 7.8nm roughness develops during subsequent SiGe growths, which is slightly less than the 10.3nm value for SiGe without inserted Si layers. Another important issue of consideration is that inserting the strained Si layers leads to increased interaction among dislocations as shown by cross-sectional transmission electron microscopy. This study explores the possibility of using strained layers for achieving flat surfaces and illustrates the need for optimization when using this approach.

Asymmetrical quantum dot growth on tensile and compressive-strained ZnO nanowire surfaces

“…With increasing strain, the impact of the strain type on the QD energy becomes more apparent [32]. The compressive strain lowers the step energy while the tensile strain increases the step energy [33][34][35][36]. This will lead to the energy barrier, E 0 b , for compressive strained surface being larger than that for the tensile strained surface, E 00 b .…”

Integrated photonic materials for the mid‐infrared

“…While graded buffer has demonstrated considerable reduction of threading dislocation density, the strain relaxation during growth (associated with network of misfit dislocation at layer/substrate interface) has been found to cause surface roughening called cross hatch pattern depending on the final Ge content and Ge grading rate (Ge % per μm). Success in reducing surface roughness has been reported using chemical mechanical polishing (CMP) 54 and by inserting thin tensile‐strained Si layer into graded SiGe buffer layer 68 . Another limitation of this platform is the high thickness of SiGe buffer layer which causes higher manufacturing cost.…”

High-quality SiGe films grown with compositionally graded buffer layers for solar cell applications

“…In order to obtain a high-quality abrupt hetero-interface, a smooth surface morphology with minimized cross-hatch pattern amplitude is required. In order to improve the properties of SiGe thin films, various types of buffer layers have been shown to confine misfit dislocations within the buffer layers such as layers grown at low temperature [8], Si-strained layers [9,10], ion-implanted layers [11], and compositionally graded buffer layers [12,13].…”