Survey of low power techniques for ROMs

Angel, E. de; Swartzlander, Earl E.

doi:10.1145/263272.263274

Cited by 34 publications

(8 citation statements)

References 7 publications

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“…The µROM power consumption is determined, in part, by the number of bits set to '1' in the µROM [3], [5]. Thus, a transformation technique that reduces the number of µROM bits that are set to '1' potentially reduces its power consumption.…”

Section: Reducing µRom Loadingmentioning

confidence: 99%

Clustering-Based Microcode Compression

Borin

Breternitz

et al. 2006

2006 International Conference on Computer Design

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Abstract-Microcode enables programmability of (micro) architectural structures to enhance functionality and to apply patches to an existing design. As more features get added to a CPU core, the area and power costs associated with microcode increase. A recent Intel internal design targeted at low power and small footprint has estimated the costs of the microcode ROM to approach 20% of the total die area (and associated power consumption). Therefore, it is desirable to apply compression techniques to microcode.Microcode poses unique challenges for compression due to the long instruction format, the hand-coded nature of the programs and the stringent performance requirements that require fast decompression. This paper describes techniques for microcode compression that achieve significant area and power savings, while presenting a streamlined architecture that enables high throughput within the constraints of a high performance CPU. The paper presents results for microcode compression on several commercial CPU designs which demonstrates compression ratios ranging from 50% to 62%.

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Section: Reducing µRom Loadingmentioning

confidence: 99%

Clustering-Based Microcode Compression

Borin

Breternitz

et al. 2006

2006 International Conference on Computer Design

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“…Therefore, the SCCS-ROM is more robust from noises. The compared conventional ROMs are a conventional ROM (CV-ROM) [1] and a charge-sharing ROM (CS-ROM) [4]. The CV-ROM uses the low power techniques; hierarchical word line, selective precharge, NMOS precharge, diffusion programming ROM core, and etc.…”

Section: Shared-capacitor Charge-sharing Rommentioning

confidence: 99%

“…Some techniques focused to reduce the power consumption by decreasing the capacitances of bit lines and word lines [1]. They are achieved by the hierarchical word line, the selective precharge, and the minimization of non-zero terms.…”

Section: Introductionmentioning

confidence: 99%

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Low-power charge-sharing ROM using dummy bit lines

Yang

Kim

2003

Electron. Lett.

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This paper proposes a shared-capacitor charge-sharing ROM (SCCS-ROM). The SCCS-ROM reduces the swing voltage using the charge-sharing technique of the charge-sharing ROM (CS-ROM) [4]. Although the CS-ROM needs three small capacitors per output, the SCCS-ROM shares the capacitors so that it needs only three capacitors. The SCCS-ROM implements the capacitors using dummy bit lines. This not only increases noise immunity but also reduces power. The simulation results show that the SCCS-ROM reduces 8.4% power compared to the CS-ROM.

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“…That is, the array is fully coded with 0s. We note that, in reality, the array can never be more than half coded with 0s as long as the inversion technique [1] is applied to reduce the active and standby power. This, however, does affect our derivation of the worst case.…”

Section: Ground Bounce Simulationmentioning

confidence: 99%

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment

Kwai

Chou

Chang

et al.

2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)

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We present a ROM compiler programmable from via 1 to via n -2, where n is the number of metal layers. The layer on which the code via is landed can be selected by the user. With the coding being able to take place as close to the topmost metal as possible, the turnaround time for a revision is shortened. In this paper, we discuss the array assembly scheme and its impacts on the design considerations by the choice of strapping period.

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Survey of low power techniques for ROMs

Abstract: Abstract

Cited by 34 publications

References 7 publications

Clustering-Based Microcode Compression

Clustering-Based Microcode Compression

Low-power charge-sharing ROM using dummy bit lines

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment

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