Survey on Memory and Devices Disaggregation Solutions for HPC Systems

Bielski, Maciej; Pinto, Christian; Raho, Daniel; Pacalet, Renaud

doi:10.1109/cse-euc-dcabes.2016.185

Cited by 9 publications

(7 citation statements)

References 12 publications

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“…This is further motivated by the observation that many HPC applications already share memory across nodes. Later studies take the irst steps to show the promise of resource disaggregation in HPC to increase resource utilization [13,47].…”

Section: Resource Disaggregationmentioning

confidence: 99%

“…While resource disaggregation is regarded as a promising approach in HPC in addition to datacenters, there is currently no solid understanding of what range or lexibility of disaggregation HPC applications require [13,47] and what is the expected improvement of resource utilization through this approach. Without any data-driven analysis of the workload, we risk over-designing resource disaggregation that will make it not only unnecessarily expensive, but also may overly penalize application performance due to high latencies and limited communication bandwidth [34,75].…”

Section: Introductionmentioning

confidence: 99%

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A Case For Intra-rack Resource Disaggregation in HPC

Klenk

Cook

Teh

et al. 2022

ACM Trans. Archit. Code Optim.

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The expected halt of traditional technology scaling is motivating increased heterogeneity in high performance computing (HPC) systems with the emergence of numerous specialized accelerators. As heterogeneity increases, so does the risk of underutilizing expensive hardware resources if we preserve today’s rigid node configuration and reservation strategies. This has sparked interest in resource disaggregation to enable finer-grain allocation of hardware resources to applications. However, there is currently no data-driven study of what range of disaggregation is appropriate in HPC. To that end, we perform a detailed analysis of key metrics sampled in NERSC’s Cori, a production HPC system that executes a diverse open-science HPC workload. In addition, we profile a variety of deep learning applications to represent an emerging workload. We show that for a rack (cabinet) configuration and applications similar to Cori, a central processing unit (CPU) with intra-rack disaggregation has a 99.5% probability to find all resources it requires inside its rack. In addition, ideal intra-rack resource disaggregation in Cori could reduce memory and NIC resources by 5.36% to 69.01% and still satisfy the worst-case average rack utilization.

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Section: Resource Disaggregationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Case For Intra-rack Resource Disaggregation in HPC

Klenk

Cook

Teh

et al. 2022

ACM Trans. Archit. Code Optim.

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“…Several studies on memory and device disaggregation are surveyed in [13]. In addition, an alternative vision on the future directions for devices disaggregation is proposed.…”

Section: Relevant Surveysmentioning

confidence: 99%

Survey of Memory Management Techniques for HPC and Cloud Computing

Pupykina

Agosta

2019

IEEE Access

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The emergence of new classes of HPC applications and usage models, such as real-time HPC and cloud HPC, coupled with the increasingly heterogeneous nature of HPC architectures, requires a renewed investigation of memory management solutions. Traditionally, memory is shared by an operating system using segmentation and paging techniques. At the same time, new classes of applications require Quality of Service (QoS) guarantees. As such, the typical practice of reserving a subset of the supercomputer to a single application becomes less attractive, leading to the exploration of cloud technologies. In this context, a viable scenario is that of multiple applications, with different QoS levels, coexisting on the same deeply heterogeneous HPC infrastructure and sharing resources. However, for this scenario to succeed in practice, resources, including memory, need to be allocated with a vision that includes both the application requirements and the current and future state of the overall system. In this survey, challenges of memory management in HPC and Cloud Computing, different memory management systems and optimisation techniques to increase memory utilisation are discussed in detail. INDEX TERMS Clouds, high performance computing, memory management, resource management. ANNA PUPYKINA received the higher education degree in data processing and control systems engineering from Samara State Aerospace University, Russia, in 2009. She is currently pursuing the Ph.D. degree with the Politecnico di Milano, under the supervision of Prof. G. Agosta. She was with Russian State Humanitarian University (RSUH), Togliatti, and also with the Department of Applied Mathematics and Informatics, Togliatti State University (TSU). Her main research interests include runtime management algorithms and programming model extensions for deeply heterogeneous systems. GIOVANNI AGOSTA received the Laurea degree in computer engineering and the Ph.D. degree in information technology from the Politecnico di Milano, Italy, in 2000 and 2004, respectively. He is currently a tenured Researcher. He has authored more than 80 articles in international journals, conferences, and workshops. His main research interest includes compiler technology. He was a recipient of four HiPEAC Awards and three Best Paper Awards. He has been involved in eight European funded projects, since 2010, holding workpackage and task leader responsibilities. He is a Full Member of the HiPEAC Network and the Organizer of two workshops colocated with the HiPEAC Conference.

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“…The employment of disaggregated accelerator elements in DCN can lead to a significant boost in computation power for tasks such as networks analytics, deep learning or encryption. However, substantial progress towards memory disaggregation has not yet been fully materialized [11].…”

Section: Introductionmentioning

confidence: 99%

“…In DDCs, the accessing of disaggregated remote memory resources as opposed to storage and accelerator elements [9,10] has the highest demand in terms of latency (10s of nanoseconds) and required link bandwidths (100s of Gb/s) [8] since the perceived memory throughput at the application layer is highly affected by these factors. Unfortunately, today's DCNs are unable to meet these demands [8,11]. To assess the ability of the dReDBox architecture with the proposed topology for meeting these demands, the application perceived performance for accessing remote DDR4 memory resources is experimentally measured; the results suggest that the proposed architecture can sustain 70% of memory throughput when accessing remote memory.…”

Section: Introductionmentioning

confidence: 99%

MCF-SMF Hybrid Low-Latency Circuit-Switched Optical Network for Disaggregated Data Centers

Saljoghei

Yuan

Mishra

et al. 2019

J. Lightwave Technol.

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This paper proposes and experimentally evaluates a fully developed novel architecture with purpose built low latency communication protocols for next generation disaggregated data centers (DDCs). In order to accommodate for capacity and latency needs of disaggregated IT elements (i.e. CPU, memory), this architecture makes use of a low latency and high capacity circuit switched optical network for interconnecting various endpoints, that are equipped with multi-channel Silicon photonic based integrated transceivers. In a move to further decrease the perceived latency between various disaggregated IT elements, this paper proposes a) a novel network topology, which cuts down the latency over the optical network by 34% while enhancing system scalability and b) channel bonding over multicore fiber (MCF) switched links to reduce head to tail latency and in turn increase sustained memory bandwidth for disaggregated remote memory. Furthermore, to reduce power consumption and enhance space efficiency, the integration of novel multi core fiber (MCF) based transceivers, fibers and optical switches are proposed and experimentally validated at the physical layer for this topology. It is shown that the integration of MCF based subsystems in this topology can bring about an improvement in energy efficiency of the optical switching layer which is above 60%. Finally, the performance of this proposed architecture and topology is evaluated experimentally at the application layer where the perceived memory throughput for accessing remote and local resources is measured and compared using electrical circuit and packet switching. The results also highlight a multi fold increase in application perceived memory throughput over the proposed DDC topology by utilization and bonding of multiple optical channels to interconnect disaggregated IT elements that can be carried over MCF links.

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Survey on Memory and Devices Disaggregation Solutions for HPC Systems

Cited by 9 publications

References 12 publications

A Case For Intra-rack Resource Disaggregation in HPC

A Case For Intra-rack Resource Disaggregation in HPC

Survey of Memory Management Techniques for HPC and Cloud Computing

MCF-SMF Hybrid Low-Latency Circuit-Switched Optical Network for Disaggregated Data Centers

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