Suzuki Stack Circuit With Differential Output

DC-biased Suzuki stack circuit for Josephson-CMOS memory applications

“…The simulation results of AC-biased interface circuit are shown in figure 2. The circuit parameters are partially selected from [7,15,22] and listed in table 1. Additionally, JJs are simulated with a Verilog-A RCSJ model in MIT Lincoln Lab SFQ5ee 10 kA cm −2 process [25].…”

“…When an SFQ pulse is received at the input terminal V in , the JJs with the critical current of I c1,4JL , I c2,4JL , and I c,SS (see figure 1 for notation) switch from superconducting to resistive states. A more detailed description of the internal switching is explained in section 2 in [15]. Since these JJs are underdamped (i.e.…”

“…Recently, several optimization techniques have been proposed for the conventional AC-biased Suzuki stack design. These techniques focus on optimizing the power dissipation [39] and differential signaling [15]. Due to the similar internal design and working principle of Suzuki stack circuit, these optimization techniques can also be applied to the proposed DC-biased design.…”

“…As compared to other types of superconductor-semiconductor interface circuits such as superconducting quantum interference device (SQUID) stack [10][11][12][13] and SFQ-to-DC converter [2,14], the Suzuki stack circuit can generate the highest output voltage in the order of tens to hundreds of mV. As a result, the CMOS amplifier stage, which is connected to the output of a Suzuki stack circuit and located at the same temperature of 4 K would require lower gain and, hence, lower power dissipation [15].…”