SVM-based real-time hardware Trojan detection for many-core platform

Kulkarni, Amey; Pino, Youngok; Mohsenin, Tinoosh

doi:10.1109/isqed.2016.7479228

Cited by 57 publications

(30 citation statements)

References 17 publications

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“…3) BUS SECURITY Bus security precautions intend to provide effective countermeasures against malicious on-chip traffic behaviors to ensure the security of communication and the reliability of data transmission between multiple cores in a multiprocessor SoC environment [105], [106]. The major malicious behaviors along this line include denial of service (DoS) [107], linker behavior [26], [27], and router behavior [108], which are launched by HTs implanted in links or routers. Attackers may exploit covert communication [73], [109], bus idle states [110], and peripheral interfaces [28] to disclose confidential information, tamper with communication data, interfere with normal operations, and perform DoS attacks.…”

Section: -Implantation Preventionmentioning

confidence: 99%

A Survey on Machine Learning Against Hardware Trojan Attacks: Recent Advances and Challenges

et al. 2020

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The remarkable success of machine learning (ML) in a variety of research domains has inspired academic and industrial communities to explore its potential to address hardware Trojan (HT) attacks. While numerous works have been published over the past decade, few survey papers, to the best of our knowledge, have systematically reviewed the achievements and analyzed the remaining challenges in this area. To fill this gap, this article surveys ML-based approaches against HT attacks available in the literature. In particular, we first provide a classification of all possible HT attacks and then review recent developments from four perspectives, i.e., HT detection, design-for-security (DFS), bus security, and secure architecture. Based on the review, we further discuss the lessons learned in and challenges arising from previous studies. Despite current work focusing more on chip-layer HT problems, it is notable that novel HT threats are constantly emerging and have evolved beyond chips and to the component, device, and even behavior layers, therein compromising the security and trustworthiness of the overall hardware ecosystem. Therefore, we divide the HT threats into four layers and propose a hardware Trojan defense (HTD) reference model from the perspective of the overall hardware ecosystem, therein categorizing the security threats and requirements in each layer to provide a guideline for future research in this direction.

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Section: -Implantation Preventionmentioning

confidence: 99%

A Survey on Machine Learning Against Hardware Trojan Attacks: Recent Advances and Challenges

et al. 2020

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“…DoS attacks on a many-core chip can target different components of the chip, including the memory system [15], and the network-on-chip (NoC) [16], [17]. With the help of hardware Trojans (HTs) [3], [4], [13], DoS attacks can be classified as 1) flooding attack [18], [19], where a large volume of useless packets floods a victim node and saturates it; 2) packet drop attack, where some packets are dropped or directed to some malicious nodes so that the victim node can never receive a single packet designated to it [20]; 3) privilege escalation attack [21], where an average user process is granted the privileges of a supervisor so that it can steal passwords; and 4) routing loop attack [2], where packets that pass the malicious node will be routed back to the source node, effectively blocking the source core from communicating with any other cores.…”

Section: B Dos Attackmentioning

confidence: 99%

“…Unfortunately, many-core chips are susceptible to be attacked by hardware Trojans (HT) which can be easily implanted to the chips at any stage from design to manufacturing, as chip designing and manufacturing is going global, and licensing of third party IP cores is becoming a commonplace in manycore chip designs. In contrast to a modern many-core chip with billions of transistors and complex functionalities, an HT circuit has an extremely low transistor count, making it hardly visible, and thus difficult to be detected by most known offline HT detection methods [1], [2]. If many-core devices infected with HTs finally get deployed, they can create catastrophic effects, including dangerous security breach and severe performance degradation [3], [4].…”

Section: Introductionmentioning

confidence: 99%

On a New Hardware Trojan Attack on Power Budgeting of Many Core Systems

Zhao

Wang

Jiang

et al. 2018

2018 31st IEEE International System-on-Chip Conference (SOCC)

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In this paper, we study stealthy false-data attacks that exploit the vulnerabilities of power budgeting scheme in NoC, which can cause catastrophic denial of service (DoS) effects. Essentially, when a power budget request packet is routed through a Trojan-infected network-on-chip node's router, the power budget request can be unknowingly modified. The global manager then tends to make really bad power budget allocation decisions with all the tampered power requests it received. That is, legitimate applications will be victimized with lower power budgets than what they initially asked for, and thus, could suffer serious performance degradation; malicious applications, on the other hand, may be entitled to high power budgets and thus see performance boost that they do not deserve. Our study has shown that this new type of DoS attack can be initiated and sustained by a simple hardware Trojan (HT) circuit that is extremely hard to be detected. The effects of this new DoS attack are simulated using a network model, and all the major parameters and factors that impact the attack effects are identified and quantified.

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“…In a good ML data-set, each feature must contribute to the class i.e better correlation between feature and the class, but not among the features [4] [5]. Relevant feature selection will aid both, increasing accuracy of Trojan detection and hardware implementation.…”

Section: A Feature Extraction and Optimizationmentioning

confidence: 99%

“…In-depth analysis of SVM and K-NN as Trojan Detection technique is performed in [4] [5]. To demonstrate detection accuracy for unexpected attack, the model is trained with two types of attacks, namely core spoofing and route looping attack.…”

Section: Analysis Of Machine Learning Algorithmsmentioning

confidence: 99%

Adaptive real-time Trojan detection framework through machine learning

Kulkarni

Pino

Mohsenin

2016

2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

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Hardware Trojans inserted at the time of design or fabrication by untrustworthy design house or foundry, poses important security concerns. With the increase in attacker's resources and capabilities, we can anticipate an unexpected new attack from the attacker at run-time. Therefore, the challenge is not only to reduce hardware overhead of added security feature but also to secure design from new attacks introduced at realtime. In this work, we propose a Real-time Online Learning approach for Securing many-core design. In order to prevent unexpected attacks, many-core provides feed-back to online learning algorithm based on core information and its behavior to incoming data packet. The proposed Online Learning approach updates the model run-time at each data transfer based on feed-back from many-core. For demonstration, Online Machine Learning model is initially trained with two types of (known) attacks and Trojan free router packets and then unexpected attack is introduced later at run-time. The results show that, feedback based Online Machine Learning algorithm has 8% higher overall detection accuracy and an average of 3% higher accuracy for unexpected attacks at each interval of 1000 test records than Supervised Machine Learning algorithms. The proposed feed-back based Trojan detection framework is demonstrated using a custom many-core architecture integrated with "Modified Balanced Winnow" Online Machine Learning algorithm on Xilinx Virtex-7 FPGA. Post place and route implementation results show that, secured many-core architecture requires 4 extra cycles to complete data transfer. The proposed architecture achieves 56% reduction in area and 50% less latency overhead as compared to previous published work [1]. Furthermore, we evaluate our framework for many-core platform by employing seizure detection application as a case study.

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SVM-based real-time hardware Trojan detection for many-core platform

Cited by 57 publications

References 17 publications

A Survey on Machine Learning Against Hardware Trojan Attacks: Recent Advances and Challenges

A Survey on Machine Learning Against Hardware Trojan Attacks: Recent Advances and Challenges

On a New Hardware Trojan Attack on Power Budgeting of Many Core Systems

Adaptive real-time Trojan detection framework through machine learning

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