Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power–delay budget

Sengupta, Anirban; Sedaghat, Reza

doi:10.1016/j.microrel.2015.03.010

Cited by 14 publications

(13 citation statements)

References 40 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Multi‐cycle transient fault security at behavioral level was handled in [6, 27, 28] through concurrent error detection scheme where replication of control data flow graph (CDFG) operations were performed. Once the scheduling of the dual modular redundant CDFG was generated, then specific hardware allocation rules were imposed to ensure detectability.…”

Section: Related Prior Workmentioning

confidence: 99%

“…Once the scheduling of the dual modular redundant CDFG was generated, then specific hardware allocation rules were imposed to ensure detectability. Sengupta and Sedaghat's approach [6] presents more comprehensive hardware allocation rules, as it encompasses the condition of minimal hardware availability as well. In other words, Sengupta and Sedaghat's approach [6] can provide multi‐cycle fault security even with the availability of single hardware type which is not possible in [28].…”

Section: Related Prior Workmentioning

confidence: 99%

“…Sengupta and Sedaghat's approach [6] presents more comprehensive hardware allocation rules, as it encompasses the condition of minimal hardware availability as well. In other words, Sengupta and Sedaghat's approach [6] can provide multi‐cycle fault security even with the availability of single hardware type which is not possible in [28]. In [28] minimum two distinctive hardware is obligatory for allocation to sister operations of original and duplicate unit in DMR.…”

Section: Related Prior Workmentioning

confidence: 99%

“…Transient faults can be exploited to create security vulnerabilities such as affecting output computational value. More explicitly, standard vulnerability arising from a transient fault results into erroneous output value due to bit flips causing catastrophic consequences on the systems [1, 4–10].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Particle swarm optimisation driven low cost single event transient fault secured design during architectural synthesis

Sengupta

Kachave

2017

J. eng.

Self Cite

View full text Add to dashboard Cite

Section: Related Prior Workmentioning

confidence: 99%

Section: Related Prior Workmentioning

confidence: 99%

Section: Related Prior Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Particle swarm optimisation driven low cost single event transient fault secured design during architectural synthesis

Sengupta

Kachave

2017

J. eng.

Self Cite

View full text Add to dashboard Cite

“…In PSO-DSE, each dimension (d) of a particle position X i (except the last dimension) is updated using the following function [33], [36]:…”

Section: ) Particle Movement Using Velocitymentioning

confidence: 99%

Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis

Sengupta

Bhadauria

2016

IEEE Access

Self Cite

View full text Add to dashboard Cite

The challenges in the current design process for consumer electronics products include greater complexity and stiff time-to-market pressure, which has led to the usage of reusable intellectual property (IP) cores (such as JPEG and MPEG) as a sustainable solution. This has led to the domain of IP protection for anti-piracy as an important subject of research for a system design. Watermarking is expected to provide the best protection of authorship when applied at higher levels, i.e., during high-level synthesis. It is also well acknowledged that watermark insertion is non-trivial, as it is very difficult to choose a strong signature that results in higher security and less area overhead among available design solutions. This paper presents a novel multi-variable signature encoding for embedding a dynamic watermark in an IP design during architectural synthesis that provides enhanced security against typical attacks. Owing to the involvement of multiple (four) variables in the proposed signature, it is difficult to realize the signature without complete encoding knowledge of the four variables. Second, our approach aims to optimize the embedding cost of the watermark by exploring a low-cost solution through particle swarm optimization-driven design space exploration based on area-delay constraints. Comparison with a recent technique indicated that our watermark incurs lower embedding cost, lower runtime, and less storage hardware.INDEX TERMS IP security, watermark, design abstraction, high level synthesis, design space exploration, particle swarm optimization, optimization, area-delay constraints.

show abstract

Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis

Sengupta

Kachave

2018

Future Generation Computer Systems

View full text Add to dashboard Cite

Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power–delay budget

Cited by 14 publications

References 40 publications

Particle swarm optimisation driven low cost single event transient fault secured design during architectural synthesis

Particle swarm optimisation driven low cost single event transient fault secured design during architectural synthesis

Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis

Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis

Contact Info

Product

Resources

About