Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

Abstract

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm2 and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling.

Single pairing spike-timing dependent plasticity in BiFeO3 memristors with a time window of 25 ms to 125 μs

“…Compared to neuromorphic approaches, all memristive approaches are several orders of magnitude better (Azghadi et al, 2014 ). In terms of absolute area, the BFO memristor is comparable to some neuromorphic implementations (Hasler and Marr, 2013 ; Noack et al, 2015 ), but not competitive with memristor crossbar devices, as we are employing a single device test structure that has a large contact size for reasons of convenience. However, BFO device scaling is well established, thus we can aggressively scale the size of the top electrode to 10 μm 2 and the thickness of the BFO to 100 nm (Jin et al, 2014 ).…”

Pulse Shape and Timing Dependence on the Spike-Timing Dependent Plasticity Response of Ion-Conducting Memristors as Synapses

“…For example, a switched-capacitor realization of synapses in 28 nm CMOS was developed (Noack et al, 2015), which minimizes the leakage current problems present when CMOS-based architectures are scaled down in size. However, this system requires 0.36 mm 2 area and a power consumption of 1.9 mW for only 128 presynapses and 8,192 “stop-learning” synapses which corresponds to roughly 2.27 × 10 4 synapses/mm 2 and an energy requirement of 0.23 nJ to 0.23 mJ per synapse.…”

“…The spike-timing dependent plasticity (STDP) synaptic learning rule, inspired from the behavior of the biological neural system (Dayan and Abbott, 2001) and dominant in the brain, has been proposed and experimentally demonstrated with memristors acting as synapses by several groups over the past few years in many material systems, such as oxides (Yu et al, 2011; Wang et al, 2012a,b, 2016; Wu et al, 2012; Pickett et al, 2013; Mandal et al, 2014; Kim et al, 2015), chalcogenides (Li et al, 2013b; Mahalanabis et al, 2014a,b, 2016; La Barbera et al, 2015), silicon (Jo et al, 2010; Subramaniam et al, 2013), organic materials (Alibart et al, 2012; Li et al, 2013a; Cabaret et al, 2014; Luo et al, 2015), and even magnetic tunnel junctions (Krzysteczko et al, 2012). Illustrations of memristor effectiveness have also been shown in simulation and with transistor and/or complementary metal oxide semiconductor (CMOS)-based memristors (Rachmuth et al, 2011; Rose et al, 2011a,b; Cruz-Albrecht et al, 2012; Noack et al, 2015) and graphics processing units (Snider et al, 2011). The exploration of new memristor materials systems is driven by the advantage of analog, memristor-based learning implementations compared to the digital-based learning, where the analog, memristor-based learning was shown to provide an improvement of at least a factor of 10 for power and density (Rajendran et al, 2013) over digital-based learning.…”

A fixed point exponential function accelerator for a neuromorphic many-core system

“…The OTA-C approach uses a transconductance to emulate an RC decay [3], [4]. In deep submicron technologies, solutions have to be found that rely less on analog performance, such as a switched capacitor charge sharing emulating an exponential decay [5]. However, the above approaches have four main drawbacks.…”