Switching and Short-Circuit Performance of 27 nm Gate Oxide, 650 V SiC Planar-Gate MOSFETs with 10 to 15 V Gate Drive Voltage

Agarwal, Aditi; Kanale, Ajit; Han, Kijeong; Baliga, B. Jayant

doi:10.1109/ispsd46842.2020.9170151

Cited by 9 publications

(7 citation statements)

References 8 publications

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“…NPN BJT activation during short-circuit measurements has also been reported in 3.3 kV SiC MOSFETs [8]. Other studies have also shown that gate oxide failure is a specific failure point in SiC MOSFETs [9][10][11][12][13][14]. High electric fields and lattice temperature during short circuits can cause gate oxide breakdown due to large leakage currents.…”

Section: Introductionmentioning

confidence: 80%

Performance of Parallel Connected SiC MOSFETs under Short Circuits Conditions

Mendy

Agbo

et al. 2021

Energies

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This paper investigates the impact of parameter variation between parallel connected SiC MOSFETs on short circuit (SC) performance. SC tests are performed on parallel connected devices with different switching rates, junction temperatures and threshold voltages (VTH). The results show that VTH variation is the most critical factor affecting reduced robustness of parallel devices under SC. The SC current conducted per device is shown to increase under parallel connection compared to single device measurements. VTH shift from bias–temperature–instability (BTI) is known to occur in SiC MOSFETs, hence this paper combines BTI and SC tests. The results show that a positive VGS stress on the gate before the SC measurement reduces the peak SC current by a magnitude that is proportional to VGS stress time. Repeating the measurements at elevated temperatures reduces the time dependency of the VTH shift, thereby indicating thermal acceleration of negative charge trapping. VTH recovery is also observed using SC measurements. Similar measurements are performed on Si IGBTs with no observable impact of VGS stress on SC measurements. In conclusion, a test methodology for investigating the impact of BTI on SC characteristics is presented along with key results showing the electrothermal dynamics of parallel devices under SC conditions.

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Section: Introductionmentioning

confidence: 80%

Performance of Parallel Connected SiC MOSFETs under Short Circuits Conditions

Mendy

Agbo

et al. 2021

Energies

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“…Overall, we can note damage or failure temperature was decreased (1) from one method to another; tively: 1320 °C, 1207 °C, 1056 °C); which allowed the device to withstand more (respectively: 1.62 µs, 4.9 µs, 9.6 µs). It is also remarkable to note that the damag corresponding to the strong degradation of the gate (2) is well associated with com temperature values for VDS and VGS depolarization (respectively: 1207 °C and 124 The gate leakage on the other hand is not visible under VGS depolarization, ( (3) , Ta…”

Section: Discussionmentioning

confidence: 96%

“…It is also remarkable to note that the damage mode corresponding to the strong degradation of the gate (2) is well associated with comparable temperature values for V DS and V GS depolarization (respectively: 1207 • C and 1241 • C (2) ). The gate leakage on the other hand is not visible under V GS depolarization, ( (3) , Table 2).…”

Section: Discussionmentioning

confidence: 99%

“…V DS Depolarization Method V GS Depolarization Method Conditions V Bus = 800 V, R G = 4.7 Ω, V GS = −5 V/+18 V V Bus = 600 V, R G = 47 Ω, V GS = −5 V/+18 V V Bus = 600 V, R G = 47 Ω, V GS = −5 N.V: none value, (1) first light gate-damage or failure temperature, (2) hard gate-damage temperature, (3) N.V: none value.…”

Section: [15]mentioning

confidence: 99%

“…A first approach consists in optimizing the gate geometry while remaining in usual planar structure. In [3], authors show that a thinning of the gate from 55 nm under V GS = 20 V to 27 nm under V GS = 10 V allows to increase T SCWT by 47% at the cost of only a 12% increase in T SCWT . In contrast, in [4], the authors show that a thickening of the gate from 50 nm to 85 nm allows the T SCWT to be increased by 50% but at the cost of a more penalizing increase of 30% in R DSON •cm 2 .…”

Section: Introductionmentioning

confidence: 99%

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VDS and VGS Depolarization Effect on SiC MOSFET Short-Circuit Withstand Capability Considering Partial Safe Failure-Mode

et al. 2021

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This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFET exhibiting different short-circuit failure mechanisms and improvement in reliability by VDS and VGS depolarization. The device robustness has undergone an incremental pulse under different density decreasing; either drain-source voltage or gate-driver voltage. Unlike silicon device, the SiC MOSFET failure mechanism firstly displays specific gradual gate-cracks mechanism and progressive gate-damage accumulations greater than 4 µs/9 J·cm−2. Secondly, a classical drain-source thermal runaway appears, as for silicon devices, in a time greater than 9 µs. Correlations with short-circuit energy measurements and temperature simulations are investigated. It is shown that the first mechanism is an incremental soft gate-failure-mode which can be easily used to detect and protect the device by a direct feedback on the gate-driver. Furthermore, it is highlighted that this new mechanism can be sufficiently consolidated to avoid the second drain-source mechanism which is a hard-failure-mode. For this purpose, it is proposed to sufficiently depolarize the on-state gate-drive voltage to reduce the chip heating-rate and thus to decouple the failure modes. The device is much more robust with a short-circuit withstand time higher than 10 µs, as in silicon, no risk of thermal runaway and with an acceptable penalty on RDS-ON.

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